Programs
- Ph. D. in Mechanical Engineering -
- B.Tech. in Artificial Intelligence (AI) and Data Science (Medical Engineering) - Undergraduate
Publication Type : Journal Article
Source : Proceedings of the International Conference on Communication and Electronics Systems, pp. 427-430. 2019
Url : https://ieeexplore.ieee.org/abstract/document/9002105
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Year : 2019
Abstract : In this work generating test pattern using zero suppressed binary decision diagram (ZBDD) to generate test patterns for combinational circuit has been used. The ZBDD for combinational circuits are first obtained then test patterns are generated from it, similar approach is used for fault injected ZBDD and XOR operation is performed of both the set of test patterns to generate test pattern to detect the fault. This approach will reduce the power consumption during test mode of a circuit.
Cite this Research Publication : Thomas, A., Anita, J.P, ” Test Pattern Generation to Detect Single Stuck-at Faults for Combinational Circuits Using ZBDD”, Proceedings of the International Conference on Communication and Electronics Systems, pp. 427-430. 2019