Publication

Abstract : This world is working mostly with wireless network systems, which has made data communication more sophisticated and securing the data plays a vital role. Due to this, Error Correction Codes (ECCs) have had huge demand in the real world. This paper focuses on the Low Power Line Product Code (LPC) which is an extension of the Modified Extended Hamming Error Correction Code and includes redundant bits like parity and extended parity bits in columns and rows. The LPC is a new solution of ECC which is designed with an increased error correction rate. The LPC is modified by introducing a novelty idea to decrease the number of parity bits to attain the same error correction rate. The novelty approach has given optimized and efficient results, resulting in a low-power LPC. The result is optimized with the area by a percentage of 4.66% and the total power by a percentage of 38.63%. This design is designed and verified at 90nm technology using the Cadence tool.