Publication

Abstract : This paper discusses new approaches to power consumption reduction through the use of a reflected-output Wilson current mirror level shifter (WCMLS), power gating (PG), and the stackly arranged low power on (SAPON) Transistor methodology. The decrease of the power delay product (PDP), a prevalent problem in conventional level shifters (LS) is the aim of these methods. Power efficiency is especially important for systems that use several supply voltages. This creative method reduces the power consumption by lowering the short circuit power through the usage of SAPON and reflected output techniques. Therefore, correcting the inefficiencies present in traditional WCMLS designs. Designed using employed in 45nm process with 0.4V input voltage can be up converted to an output value of 1.8V. The design achieves an exceptionally low power consumption of 26.21 nW with an overall delay of 4.9405 ns, while performing well throughout a range of input levels 0.25 V to 0.85 V and output levels 0.5 V to 3 V.