Qualification: 
M.Tech, B-Tech
anuchalil@am.amrita.edu

Anu Chalil currently serves as an Assistant Professor (Sr.Grade) at the Department of Electronics and Communication Engineering at Amrita School of Engineering, Amritapuri.

Anu Chalil obtained MTech in VLSI from Amrita Vishwa Vidyapeetham, Ettimadai Campus in 2009. She has completed her BTech from Mahatma Gandhi University College of Engineering, Thodupuzha in 2006. She is currently pursuing her PhD in Subthreshold FPGA Architecture at Amrita School of Engineering, Bangalore Campus. She has received fellowships for International VLSI Conference (VLSID) in 2017 and 2019. She has more than 10 years of teaching experience.

Publications

Publication Type: Conference Paper

Year of Publication Title

2020

Nirmal Vinod, K. V. Abhishek Neelakandan, R. Udith, K. Sayooj Devadas, K. Dinesh, Anu Chalil, and K. N. Sreehari, “Performance Evaluation of LUTs in FPGA in Different Circuit Topologies”, in 2020 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, India, 2020.[Abstract]


Field Programmable Gate Arrays (FPGAs) are the most important device in the field of electronics industry. FPGAs are pre-manufactured chips which could be modified electrically, to turn out to be practically any sort of advanced circuit or frame-work. The highlighting part of FPGA is its architecture which gives a broad idea about their programmable logic functionalities and interconnects. The programmable logic functions can be implemented through logic blocks that can be programmed. The Logic Block contains storage elements, multiplexers, and Look Up Table (LUT). The final device's performance and other characteristics are governed by the quality and condition of the architecture of FPGA as well as its elements. In this project, we design the LUT architecture using different circuit topologies to obtain the smallest Power delay product (PDP) value.

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2020

V. Akshaya, K. N. Sreehari, and Anu Chalil, “VLSI Implementation of Turbo Coder for LTE using Verilog HDL”, in 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, India, 2020.[Abstract]


Turbo codes are error correction codes that are widely used in communication systems. Turbo codes exhibits high error correction capability as compared with other error correction codes. This paper proposes a Very Large Scale Integration (VLSI) architecture for the implementation of Turbo decoder. Soft-in-soft out decoders, interleavers and deinterleavers is used in the decoder side which employs Maximum-a-Posteriori (MAP) algorithm. The number of iterations required to decode the information bits being transmitted is reduced by the use of MAP algorithm. For the encoder part, this paper uses a system which contains two Recursive convolutional encoders along with pseudorandom interleaver in encoder side. The Turbo encoding and decoding is done using Octave, Xilinx Vivado, Cadence tools. The system is implemented and synthesized in Application Specific Integrated Circuit (ASIC).Timing analysis has been done and GDSII file has been generated.

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2019

A. A. Kumar and Anu Chalil, “Performance Analysis of 6T SRAM Cell on Planar and FinFET Technology”, in 2019 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, India, 2019.[Abstract]


Embedded SRAM cell have become an immanent part in modern SoCs because of the faster memory operation and lower power consumption.As CMOS devices scaling down, there will be a lot of consequences such as short channel effects which will affect the device performance. FinFET technology a technology to overcome the effects of short channel effects by giving better control for gate over the channel and to improve the performance of 6T Static Random Access Memory (SRAM) circuit design. The purpose of this study is to simulate and evaluate the performance of planar and FinFET-based 6T SRAM cell and compare their results. The factors considering in this paper to observe the performance of SRAM are SNM, write margin, read current, leakage and standby leakage.The stability of SRAM bit cell is determined by static noise margin analysis, by butterfly method. Here for all the analysis and simulations Hspice is used in 16nm technology.

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2018

G. Dath and Anu Chalil, “FPGA Implementation of Physical Layer Data Encoding Schemes”, in 2018 Second International Conference on Inventive Communication and Computational Technologies (ICICCT), 2018.[Abstract]


In the fields of cellular communication and networking, transmission of digitized information requires a data encoding scheme efficient in terms of bandwidth and synchronization. Line coding is a widely accepted digitizing data encoding scheme. This paper presents the advantages of line coding schemes as developed for the modern-day use with Mentor Graphics ModelSim Edition 10.4a. Different line coding schemes are compared along with functional verification of their algorithms using the Xilinx design tool. The FPGA parameters like LUTs, I/O blocks, power, delay and frequency are compared.

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2018

G. G. Dath, Anu Chalil, and Joseph, J., “An Efficient Fault Detection Scheme for Advanced Encryption Standard”, in 2018 3rd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, India, 2018.[Abstract]


AES (Advanced Encryption Standard) is one of the widely accepted and used algorithms for ensuring the security of data. The advancements in VLSI technology, both from the point of view of design complexity and increase in the probability of error occurrences, have become a significant problem to consider. However, some faults may occur during the implementation of AES which results in reducing the reliability and may cause leakage of information. In this work, we have implemented AES-128 with fault detection techniques based on parity and interleaved parity generation which does not require any additional hardware.

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2018

J. Joseph, Anu Chalil, and Dath, G. G., “Publicly Verifiable Digital Watermarking Technique for Copyright Property Protection”, in 2018 3rd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, India, 2018.[Abstract]


Since digital images are very susceptible to manipulations and alterations, a variety of security problems are introduced. Another common application is resolving ownership disputes when copyrighted material is distributed illegally. The objective of this paper is to avoid these problems by embedding a secret, invisible watermark (WM) in images. This proposes two publicly verifiable digital watermarking techniques for copyright property protection which includes the Secure Hash Algorithm (SHA) with chaos based random number generation and the other with Least Significant Bit(LSB) with data matrix techniques. With the comparison of these two watermarking techniques, the copyright information extracted from the watermark has good quality, less hardware complexity and is robust to various attacks.

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2017

P. Chandran, Anu Chalil, and Pradeepkumar, P., “FPGA based ToF measurement system for ultrasonic anemometer”, in 2017 2nd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2017.[Abstract]


The paper describes a way of measuring the wind speed and direction based on Time of Flight. The system uses ultrasonic sound to detect the velocity of the wind. Time of Flight (ToF) is explained as the time taken by the ultrasonic sound waves to travel from one sensor to the other is defined. The propagation of these ultrasonic sound waves is affected by the intensity and direction of wind. If the direction of propagation of wind a n d the direction of propagation of sound is same, the ToF will be less. The lesser the ToF, more is the wind velocity. The system mainly includes Ultrasonic Transceiver, Time to Digital Converters (TDC), Multiplexer, FPGA and user interface. The FPGA communicates with the TDC and multiplexer using SPI protocol. FPGA plays a crucial role in this system. All the control and processing are done using FPGA. The proposed architecture is simulated in Libero IDE and synthesized using Synplify Pro for ProASIC3E Actel FPGA.

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2017

Anu Chalil, “Implementation of power estimation methodology for intellectual property at SoC level”, in 2017 2nd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2017.[Abstract]


In VLSI design flow, the designer has better control over critical parameters such as power consumption and delay at higher levels of abstraction. Trade-offs and design changes are easier to accomplish at architectural and system levels. The decisions taken at these levels have a large impact on the final quality of the design. Power consumption has become a vital issue in all modern designs. However, actual information on this important metric is available only after the back-end phase when the design is committed to silicon. At this juncture, very little can be done to optimize power. Therefore, power estimation at higher levels is an extremely crucial step in executing power aware designs. Power estimation techniques can be applied at all abstraction levels in the low power design flow, of which highest level is system level. The design process at higher abstraction level shields the designer's crucial time and effort in power estimation. It is challenging to extract and analyse knowledge about the circuit of the system at the system level. If we estimate the power at this level, large power savings can be done and also power optimized design changes can be done. This paper describes an augmented power estimation methodology for intellectual property (IP) components. The method uses statistical methods to isolate a set of input influencing the output power for a particular mode of operation. The power model is developed as a function of parameters such as signal probability, transition density and spatial correlation. The proposed method was evaluated on a SDRAM controller core. The power estimation error varies from 0.3% to 12.5%.

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2017

C. Anoop and Anu Chalil, “Performance analysis of montgomery multiplier”, in 2017 2nd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2017.[Abstract]


Secure transmission of data in a system over the network makes use of various cryptographic techniques. A good and efficient cryptosystem would play a crucial role in providing security services as Data-integrity, Confidentiality, and Authenticity. The security aspect of a cryptosystem is dependent on the computational difficulty involved in solving the mathematical problems involved in the cryptographic technique. Modular exponentiation which makes use of repeated modular multiplication is a tedious process, which is the core operation utilized in cryptosystems. So one can say that the performance of a cryptosystem confides in the performance of modular multiplication and exponentiation. Montgomery multiplication is considered to be a method for performing fast modular multiplication. In this paper comparative study of Montgomery multiplier for various bits is carried out by implementing in Spartan 3E FPGA board and it's different parameters are categorically analyzed.

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2014

J. Merin Philip and Anu Chalil, “An FPGA Implementation of linear & Circular Convolution”, in IEEE National Conference on Electrical & Electronics Engineering (NC3E-2014), Banglore, 2014.

Publication Type: Conference Proceedings

Year of Publication Title

2020

Syam Krishnan T., Anu Chalil, and K. N. Sreehari, “VLSI Implementation of Reed Solomon Codes”, 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC). pp. 280-284, 2020.[Abstract]


Reed Solomon(RS) codes are error correction codes that are widely used in communication systems. RS codes exhibits high error correction capability as compared with other error correction codes. Encoding is the process of adding parity bits to the input messages. The input message and parity bit together form the codeword. The input of the decoder can contain errors. In decoding, the original message is retrieved by applying different algorithms to the codeword. This paper uses LFSR for encoding and the Peterson Gorenstein Zierler algorithm for decoding. This work is aimed at execution of RS codes using different technologies. The Reed Solomon encoding and decoding is done using Octave, Vivado, Cadence tools. The data is tested for a single error and two errors. The system is implemented and synthesized in Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA). Timing analysis has been done and GDSII file has been generated.

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Publication Type: Journal Article

Year of Publication Title

2018

J. Joseph and Anu Chalil, “Performance Evaluation Based on Placement Planning of Logic Blocks in FPGA Design”, 2018 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), pp. 1-4, 2018.[Abstract]


The Field Programmable Gate Arrays (FPGAs) show reasonable improvements in the speed and power constraints which makes a platform for the digital circuits implementations. For designing an FPGA, synthesis tools are used which performs various minimizations and optimizations techniques. The synthesis tools use the RTL representation of the design with a set of timing constraints and generate the corresponding gate-level netlists. Today, the most advanced Xilinx Vivado Design Suite is used for the FPGA design as a synthesis tool. In some cases, the Xilinx Vivado can’t meet the designer’s required delay and power constraints. So the main aim of this project is to evaluate the improvements in performance by planning the placements of the logic blocks to meet the required speed and power constraints of the designer in Xilinx Vivado software

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