Qualification: 
M.Tech
sp_kirti@blr.amrita.edu

Kirti S. Pande currently serves as Assistant Professor(Sr.Gr) at department of Electronics and Communication,Amrita School of Engineering. She is currently pursuing her Ph. D.

Publications

Publication Type: Conference Paper

Year of Publication Publication Type Title

2015

Conference Paper

S. Mohan, Pande, K. S., and Dr. N.S. Murty, “Stability investigation for 1R-2W and 2R-2W Register File SRAM bit cell using FinFET in subthreshold region”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.[Abstract]


Register Files (RF) are multi-port static memories with dedicated READ and WRITE ports for high bandwidth memory operations. The Register Files are important components in today's devices like Central Processing Unit (CPU) and Network Routers. Low power and area critical RF memories use SRAMs rather than the latches/flip-flops as the building block. Due to lack of performance and short channel effects, scaling of conventional MOSFETs towards Deep Submicron (DSM) dimensions in memories as well as in other System-on-Chip (SoC) designs became tedious. Recently in DSM designs, the conventional planar MOSFETs are being replaced by thin body FinFETs because of their better subthreshold swing, reduced short channel effects and better scalability. This paper proposes a 6T subthreshold 1R-2W SRAM and 8T 2R-2W SRAM bit cell designs using 25nm FinFET transistors having independent READ and WRITE ports. The proposed structures are with reduced leakage power and also show improved read stability and write stability as compared to the conventional single port SRAM structure. © 2015 IEEE.

More »»

2015

Conference Paper

P. Sreelakshmi, Pande, K. S., and Dr. N.S. Murty, “SRAM cell with improved stability and reduced leakage current for subthreshold region of operation”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.[Abstract]


In this paper, a Modified Differential 8T SRAM cell is proposed for subthreshold region of operation. Forward Body biasing technique is used to improve the drivability of transistors and sleep transistor logic is used to reduce the leakage current in standby mode. The proposed design is implemented with 45 nm CMOS technology and is simulated using Cadence Virtuoso Simulator. At 0.5 V supply voltage, the read SNM and write SNM are 98 mV and 112 mV respectively and these are 32% and 21% higher than there reported in literature. The leakage current and power consumption of the cell are 3.26 fA and 1.63 fW respectively. © 2015 IEEE.

More »»

2015

Conference Paper

J. Jose, Pande, K. S., and Dr. N.S. Murty, “A memory architecture using linear and nonlinear feedback shift registers for data security”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.[Abstract]


In this paper, memory architecture for ensuring data security is proposed. A Graphical User Interface (GUI) is assumed in the work to enter user ID and password for each user authentication. Valid user will be given access to the corresponding data whereas invalid user will be given access but will receive garbage data to prevent multiple trails to break in. The architecture using Galois type Linear Feedback Shift Registers (LFSRs) as well as Nonlinear Feedback Shift Registers (NLFSRs) is implemented and verified for the functionality. The power consumption is estimated using 180nm Cadence RTL Compiler and the level of data security using the National Institute of Standards and Technology (NIST) test suite for random numbers and compared the results achieved through the two implementations. The power consumption is 2.291 mW for NLFSR type of implementation and is less than that of the LFSR type of implementation by 23.9%. It is observed that NLFSR type of implementation passes the four NIST tests and whereas the LFSR type of implementation fails in two out of the four NIST tests. © 2015 IEEE.

More »»

2015

Conference Paper

J. Parimala, Priyanka, K., Kaumudi, L. S., Pande, K. S., and Dr. N.S. Murty, “Subthreshold voltage to supply voltage level shifter using modified revised wilson current mirror”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.[Abstract]


In this paper, we present a Modified Revised Wilson Current Mirror Level Shifter (MRWCMLS) to convert subthreshold voltage to supply voltage with low leakage power. Increasing speed and complexity of today's designs resulted in increase in power consumption. System on Chip (SoC) may have few modules which are supplied with subthreshold voltage to achieve low power consumption and the remaining work with above threshold voltage supply. The level shifter which can convert subthreshold voltage level to supply voltage level is designed to minimize circuit leakage power with optimum number of transistors in the circuit. MRWCMLS has been implemented in 180 nm CMOS technology and is simulated using Cadence Virtuoso Simulator and the results are compared with the existing level shifters. In comparison with Revised Wilson Current Mirror Level Shifter (RWCMLS), the leakage power with normal transistors and with high Vth transistors type of implementation of the proposed MRWCMLS, is reduced by 34% and 43% respectively. © 2015 IEEE.

More »»
207
PROGRAMS
OFFERED
5
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
8th
RANK(INDIA):
NIRF 2018
150+
INTERNATIONAL
PARTNERS