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Publication Type : Conference Paper
Publisher : 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA),
Source : 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), IEEE, Coimbatore, India (2019)
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2019
Abstract : In DSP applications, there is a need for accumulation of the squares. In this paper,architecture for 16-bit squarer-accumulator(SQAC) is proposed and designed using folding and merging based 8-bit squarer. The carry-look-ahead adder (CLA) is used to add the squarer output to that of an accumulator. The functionality of the proposed 16-bit SQAC is analyzed using Xilinx Vivado and performance is compared with the two individual 16-bit SQAC is implemented using Radix-4 &Radix-8 based Booth multiplier at 45nm technology using Cadence Encounter RTL Compiler. The experimental results convey that area, power & delay has been diminished for the proposed SQAC by 46.55%, 48.35% & 59.82% and by 48.76%,45.34% & 51.76% as compared with SQAC using Radix-4 based Booth multiplier and SQAC using Radix-8 based Booth multiplier respectively.
Cite this Research Publication : H. M., K., N., P., M., and Pande, K. S., “SQAC Using Folding-Merging Based Squarer”, in 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2019.