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Dr. Yanamala Rama Muni Reddy

Assistant Professor, School of Artificial Intelligence, Amrita Vishwa Vidyapeetham, Coimbatore

Qualification: M. Tech, Ph.D
yrm_reddy@cb.amrita.edu
ORCID ID
Research Interest: FPGA based Hardware Accelerator Architecture Design for Deep Learning Models

Bio Publications Qualification Experience Teaching Miscellaneous
Bio

Yanamala Rama Muni Reddy currently serves as an Assistant Professor at the School of Artificial Intelligence, Amrita Vishwa Vidyapeetham, Coimbatore Campus. He completed his Ph.D. from NIT Warangal.

Publications

Journal Article

Year : 2024

High-Speed Power Allocation in NOMA System using FPGA based DNN

Cite this Research Publication : Yanamala, Rama Muni Reddy, and Muralidhar Pullakandam. "High-Speed Power Allocation in NOMA System using FPGA based DNN." Journal of Circuits, Systems and Computers, Vol. 33, No. 14, 2420004 (2024)

Publisher : Journal of Circuits, Systems and Computers

Year : 2024

An Effective Hybrid Deep Learning Model for Single-Channel EEG-Based Subject-Independent Drowsiness Recognition

Cite this Research Publication : Reddy, Y. Rama Muni, P. Muralidhar, and M. Srinivas, "An Effective Hybrid Deep Learning Model for Single-Channel EEG-Based Subject-Independent Drowsiness Recognition," Brain Topography, Volume 37, pages 1–18, (2024)

Publisher : Brain Topography

Year : 2024

Empowering edge devices: FPGA‐based 16‐bit fixed‐point accelerator with SVD for CNN on 32‐bit memory‐limited systems

Cite this Research Publication : Yanamala, Rama Muni Reddy, and Muralidhar Pullakandam, "Empowering edge devices: FPGA‐based 16‐bit fixed‐point accelerator with SVD for CNN on 32‐bit memory‐limited systems." International Journal of Circuit Theory and Applications, DOI: 10.1002/cta.3957. (2024).

Publisher : International Journal of Circuit Theory and Applications

Year : 2023

A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device

Cite this Research Publication : Yanamala, Rama Muni Reddy, and Muralidhar Pullakandam. "A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device." Design Automation for Embedded Systems, Volume 27, pages 165–189, (2023)

Publisher : Design Automation for Embedded Systems

Conference Paper

Year : 2024

FPGA (ZCU104) Based Energy Efficient Accelerator for MobileNet-V1

Cite this Research Publication : Yanamala, Rama Muni Reddy, and Muralidhar Pullakandam, Satyanarayana G.N.V, Jagan Dumpala, "FPGA (ZCU104) Based Energy Efficient Accelerator for MobileNet-V1," 2024 IEEE International Colloquiumon Signal Processing & Its Applications (CSPA2024). Accepted and Presented in Malaysia.

Publisher : 2024 IEEE International Colloquiumon Signal Processing & Its Applications (CSPA2024)

Year : 2023

Pipelined CORDIC Architecture Based DDFS Design and Implementation

Cite this Research Publication : Verma, Sandeep Kumar, Muralidhar Pullakandam, and Rama Muni Reddy Yanamala. "Pipelined CORDIC Architecture Based DDFS Design and Implementation." 2023 IEEE 20th India Council International Conference (INDICON). IEEE, 2023.

Publisher : 2023 IEEE 20th India Council International Conference (INDICON)

Year : 2023

Weapon Object Detection Using Quantized YOLOv8

Cite this Research Publication : Pullakandam, Muralidhar, Keshav Loya, Pranav Salota, Rama Muni Reddy Yanamala, and Pavan Kumar Javvaji. "Weapon Object Detection Using Quantized YOLOv8." In 2023 5th International Conference on Energy, Power and Environment: Towards Flexible Green Energy Technologies (ICEPE), pp. 1-5. IEEE, 2023.

Publisher : 5th International Conference on Energy, Power and Environment: Towards Flexible Green Energy Technologies (ICEPE)

Year : 2023

Pneumonia Detection Using Transfer Learning and Hardware Implementation in Edge TPU

Cite this Research Publication : Mandal, Sujay Kumar, Muralidhar Pullakandam, and Rama Muni Reddy Yanamala. "Pneumonia Detection Using Transfer Learning And Hardware Implementation in Edge TPU." 2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT). IEEE, 2023. DOI:10.1109/ICCCNT56998.2023.10308072

Publisher : 14th International Conference on Computing Communication and Networking Technologies (ICCCNT)

Year : 2022

An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device

Cite this Research Publication : Yanamala, Rama Muni Reddy, and Muralidhar Pullakandam. "An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device." 2022 IEEE International Symposium on Smart Electronic Systems (iSES). IEEE, Warangal, India, 2022, pp. 112-117, doi: 10.1109/iSES54909.2022.00033.

Publisher : 2022 IEEE International Symposium on Smart Electronic Systems (iSES). IEEE, Warangal, India

Qualification

Ph. D.

Year: 2022 – 2024 (Thesis submitted)
Specialization: FPGA based hardware accelerator architecture design for DL models
Thesis Title: DNN Acceleration using FPGA Architectures: Design Methodologies, Implementation Strategies, and Performance Analysis

M. Tech.

Year: 2016-2018
Specialization: Microelectronics and VLSI
Thesis Title: RISCV Debug Support V-0.13

Experience

Current Positions

Assistant Professor (2024)

Past Positions

SOC Design Engineer in INTEL India Pvt. Ltd.

Teaching

Courses Taught

  • Elements of Computing System 1
Miscellaneous

Membership/ Associations

  • IEEE Student Member
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