Publication Type : Journal Article
Publisher : 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI)
Campus : Coimbatore
School : School of Engineering
Department : Electrical and Electronics
Year : 2021
Abstract : The principle of redundant binary representation is used to design power and area efficient signed Vedic $8\times 8$ multiplier architecture. The Urdhva Tiryakbhyam Sutra, which extends Vedic algorithms to signed numbers has been implemented in this work. The design is written in VHDL and synthesized on FPGA device using Xilinx ISE 14.4. In contrast to the traditional architectures considered, the proposed architecture performs better in terms of power.
Cite this Research Publication : C. Mahitha, S. C. S. Ayyar, S. D. B, A. Othayoth and R. S R, "A Low Power Signed Redundant Binary Vedic Multiplier," 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI), 2021, pp. 76-81, doi: 10.1109/ICOEI51242.2021.9453032.