Publication

Abstract : This paper presents an area efficient implementation of short block length and low rate Quasi cyclic (QC)-Low Density parity check code (LDPC) encoder for binary input additive white Gaussian noise channel (BIAWGN) targeting the Ultra-reliable low-latency communication (URLLC) application. The stringent prerequisites like ultra-high reliability and lesser latency have made URLLC applications most critical feature of the 5G wireless communication. In the proposed architecture the dual diagonal encoding is used to generate the codeword. The primary building block in the dual diagonal encoding is the barrel shifter, which performs the cyclic shift operations. Thus, it occupies larger part of area next to the memory blocks. This works aims at drastically reducing the number of barrel shifters using hardware sharing technique. The implementation of the encoder for short length code is done in Xilinx Virtex-7 FPGA platform. The simulation results show that the proposed architecture can reduce the number of multiplexers in the encoder architecture by 37%, thus considerably reducing the area compared to the existing architectures.