Publication

Abstract : This paper presents the FPGA-based realization of an adaptive slot machine that incorporates dynamic threshold control to enhance gameplay variability. The internal architecture consists of a finite-state machine (FSM) for controlling game flow and a linear-feedback shift register (LFSR) for generating pseudorandom outcomes. Unlike conventional slot machines with fixed winning conditions, this design employs a feedback-driven mechanism that adjusts the win threshold in real time based on player performance, thereby simulating intelligent game behavior. The system is implemented using Verilog HDL, synthesized and analyzed in Xilinx Vivado, and verified through RTL simulation using ModelSim. The deployment on a Spartan-7 FPGA confirmed correct state transitions, real-time responsiveness, and stable adaptive operation. The design achieved less than 2 % utilization of FPGA resources and a maximum clock frequency of 137 MHz, demonstrating high efficiency. This work validates the feasibility of embedding dynamic control logic directly into digital hardware and provides a practical foundation for reconfigurable gaming platforms or instructional demonstrations of adaptive digital systems.