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Design and Implementation of an Optimized Double Precision Floating Point Divider using Cache Memory

Publication Type : Conference Paper

Publisher : Coimbatore Institute of Technology

Source : International Conference on Embedded Systems (ICES 2010) , EEE Department, Coimbatore Institute of Technology, Coimbatore (2010)

Campus : Coimbatore

School : School of Engineering

Department : Electronics and Communication

Year : 2010

Abstract :

Cite this Research Publication : S. .K and Ramesh S. R., “Design and Implementation of an Optimized Double Precision Floating Point Divider using Cache Memory”, in International Conference on Embedded Systems (ICES 2010) , EEE Department, Coimbatore Institute of Technology, Coimbatore, 2010.

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