Publication

Abstract : Efficient scheduling in digital systems is very important to make sure everything gets fair treatment, avoid situations where some tasks are never given a chance, and make the system work as fast as possible. Traditional round-robin (RR) schedulers are easy to use, but they don't work well when there are different types of tasks with varying levels of importance. Weighted Round Robin (WRR) improves fairness, but it still uses up unnecessary clock cycles when tasks are waiting. This paper introduces a better version of the WRR scheduler that handles both internal and external priorities. It uses an improved skip-ahead feature and a dynamic aging method to make things more efficient. External priorities come from system-level events and can take over other tasks when needed. Internal priorities are managed through weighted fairness and an aging system to stop tasks from being left out. The new design was created using Verilog HDL and tested on Xilinx Vivado. When compared to regular RR, WRR, and the Priority-Select Arbiter, this design performs better in terms of how well it uses clock cycles, saves power, and reduces delays. The simulation results show up to a 25 % decrease in wasted clock cycles and a 3.2 % improvement in power efficiency compared to previous methods, while still ensuring fair treatment of all tasks.