Publication

Abstract : The communication of data along System-on-Chip (SoC) hierarchies between the processing and memory units should be quick and dependable at least to be able to meet the performance requirements of the modern times. The Open Core Protocol (OCP) provides a standard interface which makes SoC design easy by separating the functional from the timing aspects. This article depicts the design and Verilog coding of a memory interface employing the extended OCP with Adaptive Burst Length Control and Error Correcting Code (ECC)-based Error Correction. The interface design includes a memory controller as the OCP Master and an ECC enabled memory as the OCP Slave. The Adaptive Burst Control changes the burst length automatically to the data traffic so the bandwidth is utilized in the best way and the number of idle cycles is minimized. The ECC block is given the capability to detect and correct single-bit errors in order to guarantee data integrity even in fast transfers. The whole system has been verified through simulations with ModelSim and the output signals represent exact timing synchronization, reduced latency, and correct data recovery in case of errors. The proposed architecture enhances speed, accuracy, and stability, making it suitable for high-performance embedded and SoC-based systems.