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Efficiency Analysis of Adder Architectures: A Comparative Study Across Various Bit Lengths

Publication Type : Conference Proceedings

Publisher : IEEE

Source : 2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS)

Url : https://doi.org/10.1109/iciteics61368.2024.10625527

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2024

Abstract : This paper delves into the application of Field Programmable Gate Arrays (FPGAs) in both the design and enhancement of adders, pivotal components within digital systems. Five widely used adder architectures - Ripple Carry Adder, Carry Skip Adder, Carry Select Adder, Carry Look Ahead Adder, and Kogge Stone Adder - undergo rigorous evaluation. Leveraging the robust capabilities of Xilinx Vivado software, a comprehensive assessment of adder performance metrics, including delay, power consumption, temperature, and area utilization, is conducted across varying bit lengths (4bit to 32bit). Furthermore, practical implementation using the Basys 3 Xilinx Artix-7TM FPGA Board is executed. This meticulous analysis facilitates the identification of the most efficient adder architecture tailored to diverse bit lengths, thereby significantly enhancing the functionality and performance of digital systems across various applications.

Cite this Research Publication : Moulik Tammana, Mantri Vardhan, Geethu R.S., Abhimanyu S, Anujith A, Efficiency Analysis of Adder Architectures: A Comparative Study Across Various Bit Lengths, 2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS), IEEE, 2024, https://doi.org/10.1109/iciteics61368.2024.10625527

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