Publication

Abstract : A hardware-enhanced Sobel edge detection algorithm on an FPGA with Verilog HDL is implemented in this paper. Grayscale image data is preprocessed with MATLAB and stored in ROM inside the FPGA.Edge detection is a basic operation in image processing, and it is vital for applications like segmentation, object detection, and scene interpretation. By the use of pipelined architecture and by bypassing external memory access, the design provides high-speed edge detection appropriate for embedded real-time vision systems. Simulations were performed on a 16x16 image using Vivado, and the results were checked against MATLAB and Python-based implementations. Resultss reveal better execution time and resource optimization, which demonstrate the feasibility of this architecture in low-power embedded applications.