Publications

Abstract : This work focuses the use of hamming 3 algorithm, for Finite State Machines (FSM) in Static RAM based FPGAs. SEUs (Single Event Upsets) can affect the proper working of FSM. This imposes an increasing problem to the reliable operation of FPGAs. For avoiding this problems automatic error correction of FSMs against SEUs is presented. The paper analyzes how single bit errors within same clock cycle can be removed by the implementation of error checking bits by using hamming 3 algorithm. When a non-permanent error occurs, this method tries to return to the design to a known state of FSM. This method is validated by using fault injection through self-test bench checking. This method can ensure reliable system operation and high system availability in the field. The proposed architecture is simulated in VCS and this structure is synthesized in synplify premier for Xilinx Virtex 7 FPGA and Altera Quartus for Cyclone V FPGA.