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Publication Type : Conference Proceedings
Publisher : Institute of Electrical and Electronics Engineers Inc.
Source : 2018 International Conference on Circuits and Systems in Digital Enterprise Technology, ICCSDET 2018, Institute of Electrical and Electronics Engineers Inc., Kerala (2018)
ISBN : 9781538605769
Keywords : Decoder architecture, Decoding, Field programmable gate arrays (FPGA), Polar codes, Processing elements, Proposed architectures, Resource utilizations, Scan chain, Single-clock-cycle, Successive cancellation .
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Verified : No
Year : 2018
Abstract : This paper presents a low complexity implementation of Successive Cancellation (SC) decoder architecture for the polar codes with scan chain for fault testing. Here a modified p-node is proposed at the last stage of SC decoder to decode 2-bits in a single clock cycle. The proposed architecture is designed and implemented on Kintex Ultrascale+ FPGA, xcku5p-ffv9676. The proposed SC decoder displayed 63% reduction in latency compared to conventional SC decoder. Implementation results displayed a significant reduction in resource utilization as well as on-chip power compared to prevailing SC decoders. © 2018 IEEE.
Cite this Research Publication : Geethu S. and Gopalakrishnan, L., “Low-Complexity Successive Cancellation Decoder with Scan Chain”, 2018 International Conference on Circuits and Systems in Digital Enterprise Technology, ICCSDET 2018. Institute of Electrical and Electronics Engineers Inc., Kerala, 2018.