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Publication Type : Conference Paper
Publisher : ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology
Source : ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, Volume 5, Kanyakumari, p.336-340 (2011)
ISBN : 9781424486779
Keywords : Algorithms, Clock gating, Computer architecture, Computer hardware, Design, Digital computers, Electric power supplies to apparatus, Iterative CORDIC, Parallel CORDIC, Pipeline processing systems, Pipelined CORDIC, Rotation, Signal processing, Vector rotation
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2011
Abstract : pCORDIC (COrdinate Rotation for Digital Computers) is a hardware efficient algorithm that can be used for the implementation of all kinds of digital signal processing architectures used in most of the processing instruments. Today, for most electronic designs, power budget is one of the most important design goals. The paper analyses clock-gating technique, a simple method for power reduction, applied to the different CORDIC architectures and compares their performance especially in three different major styles iterative, parallel and pipelined structures. The core is designed in VHDL, simulated using Modelsim simulator and Implemented using Xilinx FPGA synthesis and Synopsis ASIC synthesis tools. © 2011 IEEE./p
Cite this Research Publication : Dr. Ramesh Bhakthavatchalu and Prem, N., “Low power design techniques applied to pipelined parallel and iterative CORDIC design”, in ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, Kanyakumari, 2011, vol. 5, pp. 336-340.