Publication

Abstract : The technological advancement in recent years has lead to significantly increase the demand for embedded systems which are having the attributes of being both high-performance and energy-efficient. This requirement has lead to continuous changes and innovation in processor architectures, especially in the field of open-source platforms like RISC-V. This work is used to present a five-stage pipelined RISC-V processor which has been integrated with a lightweight instruction cache which is used to enhance performance the performance of the processor under constrained power conditions. Data hazards which arise are mitigated by employing forwarding paths, while optimized branch control logic is used to reduce the stalls which occurs in pipieline. The design proposed in this study take the help of a 4-entry direct-mapped instruction cache with the intention of improving instruction fetch efficiency there by achieving higher execution speed with minimal additional power overhead. Based on established architectural principles and validated through FPGA-based implementation, the processor proposed in this study serves both as an effective educational platform and also acts as a practical low-power solution for future embedded and also consumer electronic applications.