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Optimized FPGA Architectures for High-Speed NTT Computation

Publication Type : Conference Paper

Publisher : IEEE

Source : 2025 Fifth International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT)

Url : https://doi.org/10.1109/icaect63952.2025.10958904

Campus : Chennai

School : School of Engineering

Department : Electronics and Communication

Year : 2025

Abstract : This research paper aims to enhance the performance of Number Theoretic Transform (NTT) operations in cryptographic applications by leveraging the flexibility and parallel processing capabilities of Field Programmable Gate Arrays (FPGAs). NTT, integral to many cryptographic algorithms, often faces real-time performance challenges due to computational demands. By implementing NTT on FPGAs, this approach introduces features such as parallelism, pipelining, and dynamic memory management, significantly improving computational efficiency. The proposed architecture, utilizing 8T SRAM on the AMD Kintex 7 FPGA KC705 Kit, optimizes memory bandwidth and polynomial multiplication, resulting in a robust, high-speed implementation suitable for real-time cryptographic tasks. Simu-lation results demonstrate substantial performance gains, offering a valuable framework for future cryptographic hardware designs.

Cite this Research Publication : Chetan Harsha Lekkala, Sitadevi Bharatula, B. Naresh Kumar Reddy, K Sarangam, Optimized FPGA Architectures for High-Speed NTT Computation, 2025 Fifth International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), IEEE, 2025, https://doi.org/10.1109/icaect63952.2025.10958904

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