Publication Type : Journal Article
Publisher : Journal of VLSI Design Tools and Technology
Source : Journal of VLSI Design Tools and Technology, Volume 4, Issue 2, p.59–66 (2014)
Url : https://www.researchgate.net/profile/Pritam_Bhattacharjee4/publication/290883757_Performance_Estimation_of_VLSI_Design/links/5c846baa458515831f96f47c/Performance-Estimation-of-VLSI-Design.pdf
Keywords : Elmore Delay, Fall Time, Layout, nMOS, PMOS, Propagation Delay, Rise Time
Campus : Amritapuri
School : Department of Computer Science and Engineering, School of Engineering
Department : Computer Science
Year : 2014
Abstract : This paper explores performance estimation of VLSI design using simple RC delay model based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.
Cite this Research Publication : Arindam Sadhu, Dr. Pritam Bhattacharjee, and Sabnam Koley, “Performance Estimation of VLSI Design”, Journal of VLSI Design Tools and Technology, vol. 4, no. 2, pp. 59–66, 2014.
