Publication

Abstract : As Integrated Circuits (ICs) continue to grow in complexity, reliable and power-aware testing strategies are essential. This work presents a programmable and adaptive Linear Feedback Shift Register (LFSR) for Built-In Self-Test (BIST) applications, aimed at reducing dynamic power consumption. The proposed architecture allows users to configure both seed values and feedback polynomials, providing flexibility in test pattern generation. A toggle-count-based controller continuously monitors switching activity and dynamically transitions the LFSR into a low-power mode once a predefined threshold is exceeded. In this mode, latch-based glitch-free clock gating suppresses redundant transitions while ensuring correct operation. The design was synthesized and simulated in Xilinx Vivado for 4-, 8-, and 16-bit implementations and validated on an Artix-7 FPGA. Results show up to 18.75% reduction in dynamic power and a 9.52% decrease in total power for the 16-bit case, at the expense of modest resource overhead due to gating logic. These findings highlight a practical trade-off between power savings and area, demonstrating the potential of the proposed approach for energy-efficient BIST in resource-constrained VLSI systems.