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Run-time reconfigurable multiprocessors

Publication Type : Thesis

Source : University of Paderborn, Volume Ph. D., p.170 (2010)

Campus : Bengaluru

School : School of Engineering

Department : Computer Science

Year : 2010

Abstract : The advantage in multiprocessors is the performance speedup obtained with processorlevel parallelism. Similarly, the flexibility for application-specific adaptability is the advantage in reconfigurable architectures. To benefit from both these architectures, we present a reconfigurable multiprocessor template that combines parallelism in multiprocessors and flexibility in reconfigurable architectures. A fast, single cycle, resource efficient, run-time reconfiguration scheme accelerates customizations in the reconfigurable multiprocessor template. Based on this methodology, a four core multiprocessor called QuadroCore has been implemented on UMC's 90nm standard cells and on Xilinx's FPGA. Quadrocore is customisable and adapts to variations in granularity of parallerlism, the amount of communication between tasks, and the frequency of synchronization. To validate the advantages of this approach, a diverse set of applications has been mapped onto the QuadroCore multiprocessor. Experimental results show speedups in the range of 3 to 11 in comparison to a single processor. In addition, energy savings upto 30% were noted on account of reconfiguration. Furthermore, to steer application mapping based on power considerations, an instruction-level power model has been developed. Using this model, power-driven instruction selection introduces energy savings of upto 70% in the QudroCore multiprocessor.

Cite this Research Publication : Dr. Madhura Purnaprajna, “Run-time reconfigurable multiprocessors”, University of Paderborn, 2010.

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