Publications

Abstract : Toggle rate estimation is critical in the area of chip design, as it plays a major role in the power dissipation of a chip. This work presents a method to estimate the net toggle rate of a gate level circuit considering the effects of spatial correlation, temporal correlation and glitches and a comparison with LUT based methods is carried out. Previous works have addressed only on LUT based methods. The presence of glitches is accounted for using the timing analysis information, which is obtained using Statistical Static Timing Analysis. Accurate estimation of occurrence of glitches is crucial as it significantly increases the toggle rate. The toggle rate estimation technique using Statistical Static Timing Analysis was tested on gate level benchmark circuits and a comparison with LUT benchmarks were also carried out. The toggle rate estimated on gate level circuits show16% increase in accuracy when compared to LUT based benchmarks.