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VLSI Implementation of Level Shifter: A Review Paper

Publication Type : Conference Proceedings

Publisher : IEEE

Source : 2024 10th International Conference on Advanced Computing and Communication Systems (ICACCS)

Url : https://doi.org/10.1109/icaccs60874.2024.10717131

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2024

Abstract : Level shifters (LS) are fundamental components in modern integrated circuits, facilitating voltage translation between different domains in mixed-signal and low-power designs. This review paper presents a comprehensive analysis of Very Large-Scale Integration (VLSI) implementations of level shifters, focusing on design techniques, architectures, and performance metrics. The significance of level shifters in both analog and digital systems is discussed, emphasizing their role in ensuring compatibility and efficient signal processing. Furthermore, the continuous development of LS designs is explored in addressing challenges associated with scaling down technology nodes, enhancing energy efficiency, reducing leakage currents, and improving speed and reliability. The review also highlights the impact of LS circuits on overall system performance and efficiency. In conclusion, this paper provides valuable insights into the design and application of level shifters in modern electronic systems, paving the way for future advancements in the field.

Cite this Research Publication : Sreenidhi Prabha Rajeev, Adithya R, Baby Sreeja S D, Nandu Krishnan, Gowri Ganesh, A Niranjan, VLSI Implementation of Level Shifter: A Review Paper, 2024 10th International Conference on Advanced Computing and Communication Systems (ICACCS), IEEE, 2024, https://doi.org/10.1109/icaccs60874.2024.10717131

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