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Publications
Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges

Citation : Dr. Pritam Bhattacharjee, Prerna Rana, and Alak Majumder, “Understanding of On-Chip Power Supply N ...

Publisher :Recent Trends in Communication Networks, IntechOpen, (WoS/Book SCI),

Publications
VLSI Transistor and Interconnect Scaling Overview

Citation : Dr. Pritam Bhattacharjee and Arindam Sadhu, “VLSI Transistor and Interconnect Scaling Overview”, ...

Publisher :Journal of Electronic Design Technology

Publications
Methodology of Standard Cell Library Design in .LIB Format

Citation : Arindam Sadhu and Dr. Pritam Bhattacharjee, “Methodology of Standard Cell Library Design in .LIB F ...

Publisher :Journal of VLSI Design Tool & Technology,

Publications
Performance Estimation of VLSI Design

Citation : Arindam Sadhu, Dr. Pritam Bhattacharjee, and Sabnam Koley, “Performance Estimation of VLSI Design ...

Publisher :Journal of VLSI Design Tools and Technology

Publications
Implementation of ternary logic in QCA using SPICE macro-modeling

Citation : Dr. Pritam Bhattacharjee, Arijit Dey, Kunal Das, Swarnendu Kumar Chakraborty, and Rajat Subhra Goswa ...

Publisher :Journal of Engineering Technology (SCIE/Scopus), American Society for Engineering Education,

Publications
SPICE Modeling of LDMOSFET Transistor

Citation : Dr. Pritam Bhattacharjee, “SPICE Modeling of LDMOSFET Transistor”, Journal of Semiconductor Devi ...

Publisher :Journal of Semiconductor Devices and Circuits ISSN: 2455-3379, STM Journals

Publications
SPICE modeling for Metal Island Charged Confined Cellular Automata

Citation : Dr. Pritam Bhattacharjee and Kunal Das, “SPICE modeling for Metal Island Charged Confined Cellular ...

Publisher :Journal of Computational and Theoretical Nanoscience (Scopus)

Publications
Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell

Citation : Dr. Pritam Bhattacharjee, Kunal Das, Arijit Dey, Debashis De, and Swarnendu Kumar Chakraborty, “Es ...

Publisher :Journal of Low Power Electronics (ESCI/Scopus), American Scientific Publishers

Publications
A 23.52µW / 0.7V Multi-stage Flip-flop Architecture Steered by a LECTOR-based Gated Clock

Citation : Dr. Pritam Bhattacharjee, Alak Majumder, and Bipasha Nath, “A 23.52µW / 0.7V Multi-stage Flip-flo ...

Publisher :IEIE Transactions on Smart Processing and Computing (Scopus)

Publications
Variation aware intuitive clock gating to mitigate on-chip power supply noise

Citation : Alak Majumder and Dr. Pritam Bhattacharjee, “Variation aware intuitive clock gating to mitigate on ...

Publisher :International Journal of Electronics (SCI/SCIE/Scopus)

Publications
A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips

Citation : Alak Majumder, Dr. Pritam Bhattacharjee, and Tushar Dhabal Das, “A Novel Gating Approach to Allevi ...

Publisher :Journal of Circuits, Systems and Computers (SCIE/Scopus),

Publications
A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application

Citation : Dr. Pritam Bhattacharjee and Alak Majumder, “A Variation-Aware Robust Gated Flip-Flop for Power-Co ...

Publisher :Journal of Circuits, Systems and Computers (SCIE/Scopus)

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