Publication

Abstract : This work describes the design of a charge pump-based phase locked loop (PLL). Design is carried out using 45nm CMOS process targeted at sub-6GHz frequency range. Candence virtuoso studio is used to design the circuit. It uses a combinational circuit phase detector with transmission gates that resolves the issues of blind zone and dead zone, along with a three-stage current starved voltage-controlled oscillator (VCO). The proposed frequency synthesizer operates with a very low power dissipation of 8.05 mW from a 0.75V power supply, frequency of VCO centered at 2.5GHz, with a phase noise performance of – 127 dBc/Hz at 1 MHz offset. It is intended to achieve phase locking in the sub 6GHz frequency range for use in software defined radio (SDR) and exhibits reduced lock time of ~13.5ns, offering a percentage improvement of 32.5%.