Publication

Abstract : To diagnose cardiac problems, electrocardiogram (ECG) signals are crucial, but the signals are subject to numerous types of noise. To improve the diagnostic precision and dependability of ECG-based clinical applications, an efficient adaptive LMS (Least Mean Squares) filter must be designed for noise reduction in ECG data. Baseline drift and high-frequency noise are added during the gathering and preprocessing of ECG data. The proposed adaptive filter is designed using a novel adder using 4 × 1 MUX, 2 × 1 MUX, and basic gates. The proposed adder, multiplier, adaptive LMS filter, and FIR filter are designed using Verilog HDL, simulated, and implemented using Xilinx Vivado version 2021.2 to analyze the LUTs and power of the circuit. The proposed filter adder reduces the prime concern parameters of a design such as power and area of the circuit. The implementation results reveal that the area is reduced to 4.48% of the existing method and power is reduced to 5.53% of the existing method. These findings represent a significant step forward in hardware efficiency optimization and have the potential to have a favorable effect on clinical applications and cardiac diagnostics. © 2024 IEEE.