Publication

Abstract : Edge detection is a crucial step in computer vision, widely employed in object recognition, feature extraction, and pattern recognition applications. The Sobel operator, based on gradient techniques, is prevalent due to its effectiveness in detecting intensity changes. This paper presents a hardware implementation of the Sobel edge detection algorithm using Field Programmable Gate Arrays (FPGAs), emphasizing parallel processing and optimized memory management for real-time computations. The design is implemented using Verilog HDL on the ZedBoard (Zynq-7000) FPGA. The outcomes validate the practicability of hardware-based edge detection for real-time embedded vision applications, demonstrating its suitability for autonomous vehicles, medical imaging, and surveillance systems. Compared to existing FPGA implementations, the proposed architecture achieves over 21.5% lower dynamic power consumption and reduces LUT usage by 78.6%, thereby offering an efficient balance between performance, area, and energy efficiency.