Publication

Abstract : This paper proposes two different architectures to reduce power in wireless sensor nodes. Along with these two architectures, carry looks ahead adder logic and SAD Algorithms using folded tree architecture are also explained. The energy needed for the wireless communication is very high. Radio communication has highest energy consumption. Power parallel prefix technique is used in this paper to reduce the energy and power. Parallel prefix adders have the best performance in VLSI Design. The main aim of this paper is to design and implementation of newly proposed folded tree architecture. Trunk and twig phase are the two different phases of the folded tree architecture. The energy consumption can be significantly reduced by employing a more appropriate processing element. There are different types of computations in microcontrollers. Folded tree architecture is based on the on the node data processing. Measurements of the silicon implementation show an improvement of 10-20 × in terms of energy as compared to traditional modern micro controllers found in sensor nodes.