Publication Type : Conference Proceedings
Publisher : IEEE
Source : 2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT)
Url : https://doi.org/10.1109/iceeccot52851.2021.9708048
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2021
Abstract : In this paper, the authors implemented an 8×4 barrel shifter using two MOS logics: static CMOS and pseudo NMOS. Cadence Virtuoso is used for simulation at 90nm technology. Parameters such as power consumption, delay, Power Delay Product were calculated using the cadence Virtuoso tool. The simulation results show that the power consumption of a barrel shifter designed from Pseudo NMOS is 33.5% more efficient than the barrel shifter designed from a static CMOS-based design.
Cite this Research Publication : Jaya Sai Deepak Vudatha, Sreenidhi Prabha Rajeev, Baby Sreeja, Low Power 90 nm 8 × 4 Pseudo NMOS Barrel Shifter Design, 2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT), IEEE, 2021, https://doi.org/10.1109/iceeccot52851.2021.9708048