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Adaptive LBIST for Aging-Induced Fault Dynamics in Deep-Submicron VLSI Circuits

Publication Type : Conference Proceedings

Publisher : IEEE

Source : 2025 IEEE DELCON - International Conference on Recent Smart Technologies in Engineering for Sustainable Development

Url : https://doi.org/10.1109/delcon68055.2025.11400189

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2025

Abstract : Long-term reliability in deep-submicron technologies is increasingly compromised by aging mechanisms like NBTI, HCI, and EM, which degrade circuit timing and elevate the risk of delay-sensitive faults. Conventional logic built-in self-test (LBIST), designed for manufacturing-time defects, employs static schedules ill-suited for these evolving, in-field fault dynamics. To address this gap, this paper proposes a concept for an adaptive LBIST framework. By integrating lightweight on-chip aging monitors with a risk-driven scheduling policy, the architecture dynamically prioritizes aging-prone regions and adjusts test patterns and intervals based on real-time degradation. This adaptive approach promises to sustain high fault coverage throughout a product's lifetime with minimal overhead, significantly enhancing in-field reliability for mission-critical VLSI systems.

Cite this Research Publication : Aswinth Narayan A, Kailas Krishna K. S, Nihaal Salim, Nikhil S, Sooraj S. Kumar, Geethu R. S, Adaptive LBIST for Aging-Induced Fault Dynamics in Deep-Submicron VLSI Circuits, 2025 IEEE DELCON - International Conference on Recent Smart Technologies in Engineering for Sustainable Development, IEEE, 2025, https://doi.org/10.1109/delcon68055.2025.11400189

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