Publication

Abstract : The primary challenges in VLSI industry include performance, cost, area, and power dissipation. Among these, high levels of power usage during chip testing create a serious concern regarding reliability. This paper proposes the use of an n-bit Double-Tier Linear Feedback Shift Register (DT-LFSR) for Built-In Self-Test (BIST) applications designed to reduce power dissipation by minimizing switching activities during test pattern generation. The proposed architecture splits the conventional LFSR into two tiers with an intermediate flip-flop. Implemented and verified in Xilinx Vivado 2015.3, the DT-LFSR demonstrates a 50% reduction in bit transitions compared to traditional LFSRs, greatly reducing dynamic power consumption during testing. Experimental results on 8-bit, 16-bit, 32-bit, and 64-bit configurations confirm consistent power savings without compromising fault coverage. This method offers an area-efficient, scalable solution for low-power testing and is well suited to modern system-on-chip (SoC) designs where test power constraints are strict. The results indicate DT-LFSR as a favorable alternative for power-aware VLSI testing, improving both energy efficiency and reliability in semiconductor fabrication.