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Publication Type : Conference Paper
Publisher : 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017
Source : 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017 (2017)
Campus : Bengaluru
School : School of Engineering
Center : Electronics Communication and Instrumentation Forum (ECIF)
Department : Electronics and Communication
Year : 2017
Abstract : IP cores on a chip have been drastically increasing with technology scaling. Integration of these cores on a single chip has been a challenge and Network on Chip (NoC) is the cognitive solution to this due to its faster data transmission, smaller area and lower power consumption. Routers constitute a significant part of NoC. It is imperative to design a router that is area and power efficient. The proposed router utilizes the concept of acyclic sorting operation, which replaces the cyclic round robin arbitration to obtain a low power network on chip router architecture, and this architecture is described in detail in this paper. This design achieves 18.03% decrease in area and 24.27% decrease in power with a marginal 16.41 % increase in delay when compared with the Shield router architecture.
Cite this Research Publication : O. L. M. Srrayvinya, M. Vinodhini, and Dr. N.S. Murty, “A Unique Low Power Network-an-Chip Virtual Channel Router”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, 2017.