Publications

Abstract : SoC (System on Chip) designs have become increasingly complex and dense containing multiple subsystems. Functional verification of such multi-block systems demands the need for a highly reusable and scalable testbench. Universal Verification Methodology (UVM) test bench addresses these needs with some challenges. In a traditional UVM testbench, each signal on every block needs to be reconnected to its interfaces in a system testbench. But, this task becomes ominous when there are multiple blocks with many signals requiring reconnections. Such connections also limit the ability to inject stimulus into any portion or block within the system. Enhanced UVM Harness technique provides a solution to these challenges. With this approach, connections made in a block-level test bench can be reused in a multi-block testbench and specific blocks within the system can be tested without any changes to testbench. In this paper we have applied enhanced UVM Harness technique to verification of AXI based DMA Memory system and demonstrated verification of a specific portion - AXI based Memory without changes to testbench. We have analyzed the benefits and challenges in enhancing an existing UVM based testbench to support Harness technique.