Publication Type : Conference Paper
Publisher : IEEE
Url : https://doi.org/10.1109/ICEFEET64463.2024.10866691
Keywords : Energy consumption;Microprocessors;Quantum dots;Memory architecture;Random access memory;Automata;Nanoscale devices;Power dissipation;Optimization;Switching circuits;Decoder;Multiplexer;Random Access Memory;Quantum Dot Cellular Automata;QCA Clock
Campus : Coimbatore
School : School of Engineering
Year : 2024
Abstract : The nanoscale transistor-less design of Quantum-dot Cellular Automata (QCA) technology has garnered significant attention due to its inherent advantages such as small size, rapid switching, and remarkably low energy consumption. Among its various applications in digital systems, the design and optimization of Random Access Memory (RAM) architectures stand out as particularly important. This work proposes a 1x4 RAM configuration suitable for constructing efficient single-layer QCA-based circuit. The RAM design comprises of a decoder and MUX-based nano-scale memory cell. Validation of circuit designs is conducted using QCA Designer, demonstrating the effectiveness of the proposed QCA-based RAM in terms of key performance parameters including cell count, area efficiency, latency and power dissipation. The cell count and area has decreased to 50% and 30% compared to the previous design.
Cite this Research Publication : Gopireddy Shanmukha Reddy, Maddina Sai Roopesh, Vutukuru Sai Sasidhar, Yesuri Bharat, Ramesh S R, Design of RAM Structure using Quantum Dot Cellular Automata, [source], IEEE, 2024, https://doi.org/10.1109/ICEFEET64463.2024.10866691