Publications

Abstract : The recent trend in developing embedded systems tends towards the many-core processors. The essence of the many-core can be experienced only when the communication and the allocation of the packets to different cores are considered and optimised. The increase in the number of cores within a semiconductor chip increases the complexity of the communication between the cores. The cores need to communicate to share the data in their cache instead of accessing the data from main memory. The major hindrance in the development of an effective communication system for inter-core communication is the phenomenon of congestion. The proposed work is to detect the congestion before a router causes further bottleneck for communication, rather than managing the congestion. The delay incurred by a router for processing a flit can be found by counting the number of clock cycles elapsed during the flits lifecycle on that router. A threshold on the delay may imply the upcoming congestion on the router. This delay can be useful for finding the idleness and activeness of routers. Identifying the router congestion in a many-core processor can later be useful for effective routing by managing the congestion. These results can be extended further for analysing the effects of congestion on various applications and also for developing routing techniques that can improve the multicore performance. The work uses Booksim2 simulator to analyse the system characteristics.