Publication

Abstract : VLSI integrates thousands of transistors on a chip. Safeguarding digital chips from Hardware Trojan attacks is crucial, but RTL-level detection methods remain underdeveloped compared to other Trojan insertion stages. This work focuses on a Machine Learning (ML) based approach for detecting Hardware Trojans at the Register Transfer Level (RTL) by utilizing conditional statements from Verilog code as features of the trojan circuits. The branches of conditional statements are calculated with the probabilities of them to trigger the trojan, which makes the features extracted out of these to prepare a better machine learning model for detection. The proposed method is modified by using unsupervised learning techniques to train the model and obtain better results. Alongside the model being evaluated using Trust-Hub benchmarks, a well-established suite for testing hardware security solutions, few of regularly used circuits are also used as inputs to the design to make them independent only on a few specified ranges of circuits. Using variety of unique feature selection and feature scaling techniques, the most appropriate methodology is identified, which significantly enhances the accuracy of model detection. This comprehensive approach involves meticulously analyzing and selecting the most relevant features, as well as applying the most effective scaling methods to ensure that the model performs optimally. By leveraging these advanced techniques, the model can achieve superior detection accuracy, improve True Positive Rate (TPR) and reduce false predictions, making it highly efficient.