Publication

Abstract : The Fast Fourier Transform (FFT) is a crucial algorithm in digital signal processing (DSP) applications, where the efficiency of the underlying multiplier architecture is important for implementation. The existing work is a study of FFT using Vedic and Booth multipliers to examine tradeoffs between speed and power. Building on that foundation, this work presents an enhanced and robust VLSI implementation of the FFT using Booth, Vedic, and Wallace tree multipliers, designed entirely in Verilog HDL and synthesized on the Basys-3 FPGA platform using Xilinx Vivado. The proposed designs are optimized to minimize power consumption, delay, and hardware resource utilization. All these while preserving computational accuracy. Experimental results from post-synthesis power analysis show that the optimized FFT architectures achieve notable improvements compared to earlier implementations. The Wallace tree FFT achieved the lowest delay and total on-chip power of 0.334 W while the Vedic FFT provided balanced performance with moderate power and area usage. The Booth FFT consumed the highest power of 4.781 W and the reason being its complex signed arithmetic. These results validate that optimized multiplier architectures can substantially improve FFT performance, making them ideal for low-power, high-speed VLSI signal processing applications.