Publication Type : Conference Proceedings
Publisher : IEEE
Source : 2025 IEEE 5th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
Url : https://doi.org/10.1109/vlsisata65374.2025.11070121
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2025
Abstract : This work presents the implementation of a quadrature VCO with suppressed phase noise, employing an in-phase injection-coupled topology (IPIC-QVCO). The design uses cross-coupled NMOSFETs to generate negative conductance, compensating for the tank circuit's resistive losses, while complementary cross-coupled PMOS devices are integrated to improve phase noise performance. It is implemented using a 45nm CMOS process. The phase noise at a carrier frequency of 4.9 GHz is -124.43 dBc/Hz at a 1 MHz offset. The output RF power at the fundamental frequency is 8.7 dBm, while the second and third harmonics are -23.91 dBm and -39.59 dBm, respectively. A phase mismatch of 5.0 degrees is observed between the in-phase and quadrature-phase signals. The power consumption of the QVCO at a 1.2V supply voltage is 5 mW. The peak amplitude of the in-phase and quadrature outputs is approximately 862.13 mV. An FOM value of 195.24 dBc/Hz is achieved through performance evaluation.
Cite this Research Publication : Vignesh V, Sreeja Kochuvila, Navin Kumar, QVCO Design in 45nm CMOS for Wideband Wireless Applications, 2025 IEEE 5th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA), IEEE, 2025, https://doi.org/10.1109/vlsisata65374.2025.11070121