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Publication Type : Conference Proceedings
Publisher : 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI)
Source : 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI), p.2241-2245 (2017)
Keywords : Clocks, Complexity theory, Delays, Design parameters, Field programmable gate arrays, FPGA, Hardware, Latches, LNS, LNS arithmetic unit, logarithmic number system arithmetic unit, Logic design, Low power implementation, low-power electronics, LSB, LSB technique, LUT, LUT partitioning, MSB, MSB technique, partitioned memory, Power dissipation, power reduction, sub-LUT, Table lookup, VLSI, VLSI implementation, Xilinx ISE
Campus : Coimbatore
School : School of Engineering
Center : Electronics Communication and Instrumentation Forum (ECIF)
Department : Electronics and Communication
Verified : Yes
Year : 2017
Abstract : The main motto of every electronic industry is to achieve low power. An efficient way to achieve this is by adapting different architectural modifications in the design. This paper proposes low power implementation of Logarithmic Number System (LNS) arithmetic unit on a FPGA. Power reduction is achieved by partitioning technique. The influence of partitioned memory on the power dissipated and delay required for performing arithmetic operations like add and sub in LNS are measured. Two design parameters namely MSB and LSB techniques are exploited to minimize the power dissipation. Only one of the sub-LUT is activated upon each operation which depends on MSB or LSB and also on the sign of operands. The synthesis is carried out using Xilinx ISE and the hardware is implemented on ZYBO Zynq-7000 development board. A considerable amount of reduction in power was obtained
Cite this Research Publication : vV. Vinod, Eswar, K., Vishnuvardhan, P., Srikanth, G., and Ramesh S. R., “VLSI Implementation of LNS Arithmetic Unit by LUT Partitioning”, 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI). pp. 2241-2245, 2017.