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Statistics

50+

50+

Patents
20192

20192

Books
12000

12000

Book
Chapters
4219

4219

Journal
Publications /
Scopus Indexed
216

216

Conference
Proceedings
9281

9281

Other
Publications
Publications
Design of Wallace Tree Multiplier Using Counter Architecture

Authors : Dr. Ramesh S. R., Aswin T R, Ramesh S R

Publisher :IEEE

Publications
Design of Power and Area Optimized 16 – bit Multiplier

Authors : Dr. Ramesh S. R., Tushar R, Shruti Sivaramakrishnan, Ramesh S R

Publisher :IEEE

Publications
Efficient Hardware Implementation of the Sobel Operator using FPGA

Authors : Dr. Ramesh S. R., Ambagouri Nambiar, Chippada Bhanu Prakash, Goukanapalli Siddartha Reddy, S R Ramesh

Publisher :IEEE

Publications
Design and Analysis of a Cube Calculator Using QCA Technology and its Comparison with CMOS

Authors : Dr. Ramesh S. R., Nandhaguru S, Yuvan Pranav Murugesan, Ramesh S R

Publisher :IEEE

Publications
Power and Area Optimized FFT Architecture Through Multiplier-Level Hardware Design

Authors : Dr. Ramesh S. R., Ezhilkirthik, Sujith Krishna, Uday Venu Gopal, Ramesh

Publisher :IEEE

Publications
Design and Implementation of a Low Area Single-Switch Morse Code Decoder on FPGA for Assistive Technology

Authors : Dr. Ramesh S. R., Pedada Venkata Abhiram, Abhishikth Chittala, E Jagan, Ramesh S R

Publisher :IEEE

Publications
A Lightweight Ensemble Framework for Gate-Level Hardware Trojan Detection

Authors : Dr. Ramesh S. R., Maganti Shanmukha Sri Datta, Ramesh S R

Publisher :IEEE

Publications
Area-delay efficient BCD adder in quantum dot cellular automata

Authors : Dr. Ramesh S. R., Ramesh S R, Jagadeep T, Maddala Vamsi Krishna, Sista Venkata Datta Sai Abhishek, Suraj Sai Vegunta

Publisher :IOP Publishing

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