Publication

Abstract : This paper presents a simulated study on a 2D Asymmetric Gate Stack-Triple Metal Gate-All-Around (AGS-TM-GAA) Nanowire MOSFET with a SiGe-Ge-InGaAs hybrid channel, multi-work function metal gates, and optimally structured high-k dielectric stack (TiO 2 /HfO 2 /Si 3 N 4 ). The device has lightly p-doped source/drain, the highly n-doped channel and gate work functions 4.0 eV, 3.9 eV, 4.4 eV to have a greater threshold voltage stability, to lower the potential barriers and to have a better carrier injection. This has been demonstrated to be excellent electrostatic integrity, with steep conduction-band bending ≈−1.5 eV, uniform distribution of fields in the mid-channel ≈1.3–1.5 × 10 6 V m −1 and constant electron mobility ≈8–10 cm 2 Vs −1 with ATLAS simulator. The proposed device has the following highest gate-to-drain and gate-coupling capacitances C gd ≈ 7.5 × 10 −4 –2.4 × 10 −3 fF μm −1 and C gg ≈ 4.8 × 10 −3 fF μm −1 , maximum drive current I ds ≈ 5 × 10 −3 A, subthreshold slope 2.2 × 10 −4 –1.45 × 10 −3 mV dec −1 and drain conductance ∼1 × 10 −3 μS nm −1 . Short-channel effects, including the variation in threshold-voltage, and degradation of mobility and enhancement of leakage, are substantially reduced due to the GAA, asymmetric gate stack and enhanced quantum confinement. Cut-off frequency (f T ), robust FTP behavior and peak current density are high-frequency metrics that verify the suitability of the architecture to high-speed and RF applications. With CMOS technology on the verge of reaching sub-10-nm technology, the single-gate and hetero-oxide MOSFET of the past has significant short-channel effects, reduced mobility, high leakage current and poor RF stability. This literature resolves the fundamental issue of obtaining simultaneous electrostatic integrity, high drive current, low leakage and bias stable RF behavior in an aggressively- scaled nanowire platform. In contrast to the traditional DHGO and its previous forms of GAA, the proposed AGS-TM-GAA structure combines asymmetric triple-metal gate fabrication and SiGe/Ge/InGaAs hybrid channel and multi high-k dielectric stack. The proposed device has been shown, quantitatively, to have an improvement of approximately 178% in drive current over DHGO, an increase in cutoff frequency (f T ) of 10 percent, an increase in intrinsic gain of 24 percent and an increase in transconductance generation factor (TGF) of 23 percent, clearly showing a superiority in performance in terms of advanced RF and high-speed CMOS nodes.