Publication Type : Conference Proceedings
Publisher : IEEE
Url : https://doi.org/10.1109/INCET54531.2022.9824747
Keywords : Graphics;Reduced instruction set computing;Power quality;Digital signal processors;Digital signal processing;Mathematics;Hardware;Reduced Instruction Set Computer;Verilog HDL;Vedic Mathematics;Urdhva-Tiryagbhyam Sutra;low power
Campus : Coimbatore
School : School of Engineering
Year : 2022
Abstract : Multiplier unit is a key component in high-speed processor like Digital Signal processor, graphic processor. With increase in the demand for high speed, low latency, low power and low area the demand for new techniques is high. Although several multipliers like booth multipliers, have shown some improvements in these performance parameters but Vedic multiplier based on Vedic mathematics is currently in focus due to its high speed and lower power qualities. Vedic Multiplier technique is used for fast multiplication of large numbers. It is based on" UrdhvaTriyakbhyam" which is among the 16 Vedic Sutras and which was used by ancient Indian gurusandre-discovered recently from Vedas. Multiplication serves as a key hardware block in today’s technologies like Machine Learning, Deep Learning and Digital Signal Processing. Previous Vedic multiplier showed promising results to use in general purpose processor. This paper presents the designof32-bitRISCprocessorusing32-bitVedicmultiplier.
Cite this Research Publication : Suggula Naga Sai Vishnu, Abhishek Gandluru, Ramesh S R, 32-Bit RISC Processor Using VedicMultiplier, [source], IEEE, 2022, https://doi.org/10.1109/INCET54531.2022.9824747