Publication

Abstract : Urban traffic congestion continues to be a major concern, contributing to wasted time, excess fuel consumption, and environmental pollution. These challenges are often amplified by traditional fixed-time traffic signal systems that lack the ability to adapt to real-time traffic variations. This paper presents a realtime adaptive traffic signal controller implemented on an FPGA using Verilog. The system employs a deterministic, rule-based algorithm to dynamically tune green light durations based on live traffic density obtained from lane-based sensors. Each lane is monitored by three sensors that classify traffic as low, moderate, or high, enabling the FPGA to allocate green times accordingly. Leveraging the parallel processing capabilities and low latency of FPGAs, the proposed system ensures rapid decision-making, reduced vehicle idle time, and enhanced traffic throughput. The design is lightweight, scalable, hardware-efficient, and suitable for modern intelligent transportation systems. In addition to improving traffic flow, the system contributes to lower fuel wastage and reduced emissions by minimizing unnecessary idling.