Qualification: 
M.Tech
m_vinodhini@blr.amrita.edu

M. Vinodhini currently serves as Assistant Professor(Sr.Gr) at department of Electronics and Communication, Amrita School of Engineering. She is currently pursuing her Ph. D. 

Publications

Publication Type: Book Chapter

Year of Publication Title

2021

M. Vinodhini and Murty, N. S., “Transition Based Odd/Full Invert Coding Scheme for Crosstalk Avoidance and Low Power Consumption in NoC Links”, in Advances in Signal and Data Processing, S. N. Merchant, Warhade, K., and Adhikari, D., Eds. Singapore: Springer Singapore, 2021.[Abstract]


In this paper, a Transition Based Odd/Full Invert (TBO/FI) coding scheme, which focuses on crosstalk avoidance and low dynamic power consumption in NoC links is proposed. This scheme is designed and implemented at both architectural and logic level and is evaluated using synthetic traffic scenarios for both 4- and 8-wire links. All the evaluations are performed for the worst-case, the best-case, and the typical-case scenarios. TBO/FI coding scheme has the maximum reduction percentage for both the switching activities in all the cases for 4-wire link and same is true for 8-wire link except for the worst-case scenario. TBO/FI coding scheme allows NoC power savings of up to 25.5% and 40.4% for 4- and 8-wire links with worst-case scenario and with other scenarios, NoC power consumption increases. However, this increase is lower than that of other existing schemes. These results are achieved despite the NoC router area and power overheads of 117% and 50% for 4-wire and 52% and 26% for 8-wire link, respectively. NoC router area and power reduces by 16% and 30%, respectively, with increase in link width and this reduction is more compared to all other schemes.

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Publication Type: Conference Proceedings

Year of Publication Title

2021

C. Bhargavi, Nishanth, D. V. R., Nikhita, P., and M. Vinodhini, “H-Matrix Based Error Correction Codes for Memory Applications”, International Conference on Advances in Electrical, Computing, Communications and Sustainable Technologies (ICAECT 2021). Department of Electrical and Electronics Engineering, Shri Shankaracharya Group of Institutions, SSTC, Bhilai, Chhattisgarh, India, 2021.

Publication Type: Conference Paper

Year of Publication Title

2020

T. Roshini, Krishna, R. S., Reddy, P. K., and M. Vinodhini, “Improved High Speed Approximate Multiplier”, in 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2020.[Abstract]


Digital multiplication generally produces large complicated results due to its large inputs. As the applications of digital multipliers are inherently error tolerable, approximate multipliers are designed. The aim of using approximate multipliers is to reduce the size and complexity of the operation while still retaining its meaning. Compressors have a significant role in reducing the size of the intermediate or final outputs. The proposed design uses a tree compressor which contains an XOR-MUX adder. The presence of XOR-MUX adder simultaneously lessens the quantity of logic gates used and the number of inputs processed. An 8x8 multiplier design is proposed using the proposed tree compressor. This compressor reduces the delay of the multiplier by 12.6% compared to the previous multiplier which used approximate tree compressor. The accuracy is decreased by a small amount of 0.5%. Hence, this multiplier can be used for designs which require faster processing speed.

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2020

K. Nandan Kumar, Reddy, N. V. S. Anvesh, Shanmukh, P., and M. Vinodhini, “Matrix based Error Detection and Correction using Minimal Parity Bits for Memories”, in 2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), Udupi, India, 2020.[Abstract]


Advancement in Complementary Metal Oxide Semiconductor (CMOS) technology causes Multiple Cell Upsets (MCUs). Due to the radiation particles, MCUs had been a challenging issue for data storage in memory for different applications. One of the techniques which is more often used to protect memories is Error Correction Code, because of their low complexity encoding and decoding. Generally, MCUs affect adjacent bits stored in the memory. Therefore, the technique which would detect and correct the adjacent bits as many as possible would be a productive technique. The only drawback with Matrix based code is the required number of parity bits which is used to support error correction in memories is very high. To resolve the drawback, we worked to minimise the number of parity bits in this paper. The proposed technique has equal error correction capability with smaller count of parity bits as compared to other existing techniques. Total parity bits has been reduced by 30% and area, power and delay time has been reduced by 1.12%, 33.59%, 55.46% respectively. These parameters make the proposed technique an efficient and productive one for protecting memories. This technique can be used in applications which have very strict constraints Of parity bits and speed.

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2020

S. Krishna and M. Vinodhini, “Performance Analysis of Different Reduced Precision Redundancy based Full Adders”, in 2020 IEEE International Conference for Innovation in Technology (INOCON), Nagarjuna College of Engineering and Technology, Bangalore, 2020.

2020

S. .S.Varma, N. Vineela, S., G. Sree, N., and M. Vinodhini, “Nibble Based even Invert Code for Serial NoC Links”, in 4th International Conference on Electronics, Communication and Aerospace Technology (ICECA 2020), RVS Technical Campus at Hotel Arcadia, Coimbatore, Tamil Nadu, India, 2020.

2020

M. G. Sai, K. Avinash, M., L. Naidu, S. Ganesh, M. Rohith, S., and M. Vinodhini, “Diagonal Hamming Based Multi-Bit Error Detection and Correction Technique for Memories”, in 9th International Conference on Communication and Signal Processing - ICCSP 2020, Adhiparasakthi Engineering College, Melmaruvathur, India , 2020.

2020

M. Vinodhini and Dr. N.S. Murty, “Hamming Based Multiple Transient Error Correction Code for NoC Interconnect”, in Second International Conference on Advances in Electrical and Computer Technologies 2020 (ICAECT 2020), The Hotel Aloft, Coimbatore, India, 2020.

2020

K. Anupama Sa Lakshmi, M, K. A. ., Sri, K. Madhu, and M. Vinodhini, “Code with Crosstalk Avoidance and Error Correction for Network on Chip Interconnects”, in 4th International Conference on Trends in Electronics and Informatics (ICOEI 2020) , SCAD College of Engineering and Technology, Tirunelveli, India, 2020.

2019

P. Aswathy, M. Vinodhini, and Vipin, K., “Weight Based Segmentation of Scan Cells for Efficient ATPG Technique”, in 2019 3rd International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, 2019.[Abstract]


An efficient scan & ATPG technique for reducing the power consumed in the test mode is suggested in this paper. The reduction in power is achieved by reducing the switching activity during the shift operation in circuit under test . This suggested approach is based on stitching the scan cells with similar weight for logic 1 and 0's in to the same scan chain. Experiments done on ISCAS89 benchmark circuits reveled that the proposed method can achieve an average of 15% reduction in power, an average of 13% reduction in test time and an average of 29% reduction in energy with out degrading the fault coverage, performance and area.

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2019

P. G. Hitesh, Venkatesh, P., P Reddy, S. Thirumal, and M. Vinodhini, “Efficient Multi-Bit Error Tolerant design for MVM”, in 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2019.[Abstract]


Matrix based computations are a typical way to implement many day-to-day systems. In particular, matrix vector multiplication has been implemented to provide solutions to wide range of contemporary issues. The work proposed in this paper is to detect and locate errors present in the results of a matrix vector multiplication. In matrix vector multiplication, computations are run in parallel. Categorically, this work aims to provide a mechanism to use checksum, linear binary coding technique to identify underlying faults in computational results. The necessary mathematical formulations have been derived and the design is synthesised to estimate the impact of efficient multi bit error tolerance for matrix vector multiplication. It is noticed that multi bit error tolerance for matrix vector multiplication is achieved with power optimisation compared to single bit error tolerance.

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2019

T. Sai Srinat V. Reddy, G. Reddy, H. Sekhar, K. Reddy, J., and M. Vinodhini, “Fast Error Correction for Header Flit in NoC”, in 2019 International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2019.[Abstract]


To improve data reliability in NoC, extensively adopted method is the deployment of error correction codes. Errors present in the data flit are corrected by these codes and this is not applicable for correcting errors present in the header flit. So, there is a need for an coding method which will correct errors in data and also the header flit. Further, it is important to have a coding method that will decode the header flit faster compared to data flit, as header flit is used for processing the data flits. Existing single error correction and double error detection code is improved and presented in this paper to support faster error correction in header flit with retaining the same number of redundant bits. This improved code is synthesised and results are compared with existing code. The results show that the header flit are decoded faster compared to data flits as the critical path delay is reduced.

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2019

K. Pritika and M. Vinodhini, “Logic Encryption of Combinational Circuits”, in 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2019.[Abstract]


Logic encryption for combinational circuits are proposed in this paper. Logic encryption is achieved by using key gate transistors in the circuit schematic of subtractors and adders. In this work, two logic encrypted full adder and subtractor circuits and half adder and half subtractor circuits using logic encrypted gates are designed and proposed. Of the two proposed circuits for adders and subtractors, one is strong logic encrypted than the other. All the encrypted adders and subtractors are compared with conventional adders and subtractors for logic encryption level and various other parameters like area and power. The results show improvement in area and power. The proposed half adder has 42% more area and 26.02% more power and half subtractor has 50% more area and 24.4% more power than the existing circuits. The proposed full adder has 25% less area (transistor count) and 33% less power consumption and the proposed full subtractor is also better in terms of area and power consumption with 30% and 24% lesser. Even strong logic encrypted full adder and full subtractor are proposed in this work. Full adder and subtractor have 22% increase in area each and on an average 2.3% increase in power each respectively.

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2019

S. Rajagopal, M. Vinodhini, and Murty, N. S., “Multi-bit error correction coding with crosstalk avoidance using parity sharing technique for NoC”, in Proceedings - 2018 IEEE 4th International Symposium on Smart Electronic Systems, iSES 2018, 2019, pp. 249-254.[Abstract]


In the presence of crosstalk, reliable on chip communication in deep-submicron technology is becoming a major challenge. NoC (Network on Chip) interconnects in noisy environment are highly prone to random errors and burst errors. Hence, Error Correction Code (ECC) combined with noise tolerance technique is required to make the NoC communication reliable. A Multi-bit Error Correction Coding with crosstalk avoidance using Parity Sharing technique (MECCPS), which corrects (3N/4) random error bits or (3N/4) bits of burst error for a N bit input data is proposed where N=2M for M>1. Reliability in terms of probability of residual error of the coding technique, link swing voltage of the interconnects and power consumption of the NoC interconnect are calculated to determine the performance of the MECCPS technique. The MECCPS technique has 17% less area than that of Joint Crosstalk Aware Multiple Error Correction (JMEC), but slightly higher area than those of Duplicated Two-Dimensional Parities (DTDP). The probability of residual error, link swing voltage and power consumption of link of MECCPS technique are lower than that of above mentioned techniques due to higher error correction capability. There is an overhead in power and delay for the MECCPS codec when compared to above mentioned codec which can be compensated for higher error bits correction capability. © 2018 IEEE.

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2018

R. Manasa, Ganapathi Hegde, and M. Vinodhini, “Improving the Reliability of Embedded Memories using ECC and Built-In Self-Repair Techniques”, in 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), Msyuru, India, 2018.[Abstract]


System on Chip (SoC) process technology is shrinking day by day resulting in increased complexity. In the presence of faults, the reliability of embedded memories in deep submicron technology is becoming a significant challenge. Embedded Memories are highly prone to soft errors and hard faults. Hence, hard repair techniques combined with Error Correction Codes (ECCs) can improve the reliability of embedded memories. An integrated ECC and Built-In Self-Repair (BISR) technique is proposed in this paper can correct 8 faulty bits for a 16-bit input. Higher error correction and repair capability gives the higher reliability. The proposed integrated ECC and BISR has less area and more faulty bit correction capability compared to Enhanced Built -In Self-Repair (EBISR) technique.

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2018

S. U. Himaja, M. Vinodhini, and Dr. N.S. Murty, “Multi-Bit Low Redundancy Error control with Parity Sharing for NoC Interconnects”, in International Conference on Communication and Electronics Systems (ICCES) 2018, PPG Institute of Technology, Coimbatore, 2018.

2018

S. T. Teja, Narayana, T. V. V. Saty, M. Vinodhini, and Dr. N.S. Murty, “Joint Crosstalk Avoidance with Multiple Bit Error Correction Coding Technique for NoC Interconnect”, in 7th IEEE International conference on Advances in Computing, Communications and Informatics (ICACCI), PES Institute of Technology, Bengaluru, South campus, India, 2018.

2017

M. Moulika, M. Vinodhini, and Dr. N.S. Murty, “Data Flipping Coding Technique to Reduce NOC Link Power”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, Coimbatore, India, 2017.[Abstract]


Power consumed by Network on Chip (NoC) plays significant role in the power budget of the System on Chip (SoC). In NoC, links consumes almost quarter of the power. Transition count in the link have to be reduced to reduce the switching activity and hence its dynamic power. Many techniques have been introduced to reduce the transition count. This paper presents a unique data coding technique through which the transition count can be reduced in parallel data transmission. This technique reduces an average of 61.42 percentage of link power with less area compared to quadro and multi coding techniques. The proposed technique, which is applicable for any data width, achieves 17% power saving of the total network used for demonstration.

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2017

O. L. M. Srrayvinya, M. Vinodhini, and Dr. N.S. Murty, “A Unique Low Power Network-an-Chip Virtual Channel Router”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, 2017.[Abstract]


IP cores on a chip have been drastically increasing with technology scaling. Integration of these cores on a single chip has been a challenge and Network on Chip (NoC) is the cognitive solution to this due to its faster data transmission, smaller area and lower power consumption. Routers constitute a significant part of NoC. It is imperative to design a router that is area and power efficient. The proposed router utilizes the concept of acyclic sorting operation, which replaces the cyclic round robin arbitration to obtain a low power network on chip router architecture, and this architecture is described in detail in this paper. This design achieves 18.03% decrease in area and 24.27% decrease in power with a marginal 16.41 % increase in delay when compared with the Shield router architecture.

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2017

M. Vinodhini and Dr. N.S. Murty, “Merged arbitration and switching techniques for network on chip router”, in 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS), 2017.[Abstract]


In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is the router which dominants the performance of NoC. A baseline router incorporates the FIFO (First In First Out) buffers, the routing computation logic, the arbiter and the crossbar switch fabric. In this paper, we propose different techniques of merging arbitration and switching functionalities accomplished in wormhole NoC router. Proposed microarchitectures for merging these functionalities are Merged Arbitration and Switching (MAS) microarchitecture based on multiplexer reorganization, Pipelined Merged Arbitration and Switching (PMAS) microarchitecture based on Pipelining and Wave-pipelined Merged Arbitration and Switching (WMAS) microarchitecture based on Wave-pipelining. Synthesis results show that the MAS microarchitecture outperforms the Merged ARbiter and multipleXer (MARX) microarchitecture in area and power consumption by 21.8% and 39.5% respectively. Simulation results show that the PMAS and WMAS microarchitectures outperform MARX microarchitecture in throughput by 40% and 60% respectively at a marginal cost of area and power consumption. Therefore, the benefits of using MAS microarchitecture in wormhole NoC router is low area and power consumption and PMAS or WMAS microarchitecture is high throughput. More »»

2017

S. Tambatkar, Menon, S. N., Sudarshan, V., M. Vinodhini, and Dr. N.S. Murty, “Error detection and correction in semiconductor memories using 3D parity check code with hamming code”, in 2017 International Conference on Communication and Signal Processing (ICCSP), 2017.[Abstract]


Data stored in memory or buffer needs Error Detection And Correction (EDAC). Errors occur due to supply voltage fluctuations and/or noise due to electromagnetic interference or external radiation. These errors could be either temporary or permanent. In this paper, a EDAC method is proposed to detect and correct errors based on 3D parity check. In the encoder, the data bits are arranged in a matrix format and then parity bits are calculated for each row, column and diagonal. Errors present in parity bits are detected and corrected using Hamming code. Regeneration of data bits and Syndrome calculation at the decoder helps in detecting and correcting the error bits in the data. The 3D Parity check code can correct up to 3 bits of any combination of errors in the data and the Hamming code can correct up to 3 bits in the parity, if they occur in specific combinations. Thus, this method can detect and correct errors in both data and parity bits. This method achieves higher reliability by having a slight tradeoff in area and power consumption compared to other similar methods.

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2017

P. Raha, M. Vinodhini, and Dr. N.S. Murty, “Horizontal-vertical parity and diagonal hamming based soft error detection and correction for memories”, in 2017 International Conference on Computer Communication and Informatics (ICCCI), 2017.[Abstract]


External radiations create soft errors which are turning into an undeniable critical issue. Customarily, Single Error Correction (SEC) code which can detect and correct 1-bit error per memory word is used to rectify soft errors. As errors turn out to be more common, the SEC methodology becomes inefficient. In this paper, Horizontal-Vertical Parity and Diagonal Hamming (HVPDH) method is proposed for detection of up to 8-bit errors and correction of 1-bit error, all combinations of 2-bit errors and most combinations of 3, 4 and 5-bit errors for memories. The aim here is to incorporate an encoder and decoder which will be effective in detecting and correcting errors. The encoder and decoder use three parity sets, namely horizontal, vertical and grouped diagonal Hamming parities. As per the analysis, higher code rate is achieved by using HVPDH method in memories when compared to the existing methods. More »»

2015

M. Vinodhini, Lillygrace, K., and Dr. N.S. Murty, “A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.[Abstract]


This paper proposes fault tolerant Network on Chip (NoC) architecture which enables switching of error control coding scheme present in data link layer and network layer as needed, depending upon the rate of error at runtime. The proposed Joint Crosstalk Avoidance-Five Bit Error Correction-Six Bit Error Detection (JCA-FBEC-SBED) error control coding scheme is used in both the layers. This scheme provides crosstalk avoidance and also random and burst error correction up to 5 bits and detection up to 6 bits. The error detection outcomes at all routers in the path are recorded in the error information flit. With the help of error information flit, the error rate is calculated in the destination network interface. The calculated error rate is compared with two threshold values selected based upon the traffic pattern used. If the error rate is less than the lower threshold value, only network layer error control coding scheme is activated. If the error rate is in between the lower and higher threshold values then the error control scheme present in both network layer and datalink layer will be activated, but the error control scheme present in data link layer is activated only in the alternate routers present in the routing path. If the error rate crosses higher threshold value, error control coding scheme present in both the layers will be activated. The proposed JCA-FBEC-SBED error control coding scheme has higher reliability in terms of error detection and correction, when compared to other error control coding schemes with trade-off in delay, area and power consumption. The proposed router architecture has reduced delay and slight increase in area and power consumption of 2.1% and 5.8% respectively, when compared to the runtime adaptive scrubbing router. Our proposed fault tolerant NoC architecture theoretically provide higher data transfer reliability and energy efficiency when compared to other double layer runtime adaptive fault tolerant NoC architectures. The runtime adaptive error control reduces the overall power consumption of the NoC architecture even though JCA-FBEC-SBED decoder consumes more power compared to other schemes. © 2015 IEEE.

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2015

R. Louis, M. Vinodhini, and Dr. N.S. Murty, “Reliable router architecture with elastic buffer for NoC architecture”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.[Abstract]


Router is the basic building block of the interconnection network. In this paper, new router architecture with elastic buffer is proposed which is reliable and also has less area and power consumption. The proposed router architecture is based on new error detection mechanisms appropriate for dynamic NoC architectures. It considers data packet error detection, correction and also routing errors. The uniqueness of the reliable router architecture is to focus on finding error sources accurately. This technique differentiates permanent and transient errors and also protects diagonal availabilities. Input and output buffers in router architectures are replaced by elastic buffers. Routers spend considerable area and power for router buffer. In this paper the proposed router architecture replaces FIFO buffers with the elastic buffers in order to reduce area, and power consumption and also to have better performance. © 2015 IEEE.

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2015

Ha Kalwad, Neeharika, Sb, Divya, Sc, M. Vinodhini, and Dr. N.S. Murty, “Merged switch allocation and transversal with dual layer adaptive error control for Network-on-Chip switches”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.[Abstract]


In this paper, we propose a Network on Chip router architecture with increased reliability, energy efficiency and with reduced area overhead. The proposed router architecture model adjusts dynamically to the error control strengths of the layers of NoC. In this paper, we target to optimize the combined operations of arbiter and multiplexer by using a Merged Arbiter Multiplexer (MARX) along with a dual layer cooperative error control protocol. By doing so, the number of pipe line stages, area and power consumed is reduced. We use XY Routing algorithm to send data from one router to the other when these routers are placed in network architecture. The proposed model outperforms the dual layer error control model without MARX unit. The router architecture with MARX unit has 22.7% less area and 2.4% less energy consumption than router architecture without MARX unit but has moderate increase in the delay. © 2015 IEEE.

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Publication Type: Journal Article

Year of Publication Title

2020

M. Vinodhini, N. S. Murty, and Dr. T. K. Ramesh, “Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC”, IEEE Access, vol. 8, pp. 174614-174628, 2020.[Abstract]


Ensuring reliable data transmission in multicore System on Chip (SoC), which employs Network on Chip (NoC), is a challenging task. This task is well addressed by Error Correcting Codes (ECC) in on-chip as well as off-chip networks. ECC significantly improves reliability of NoC interconnects with area and power overhead. In this paper, we propose a novel Transient Error Correction (TEC) coding scheme for reliable low power data link layer in NoC to attain a high error correction capability with less hardware overhead. Performance of TEC scheme is evaluated with realistic traffic patterns and validated with simulation results. The proposed scheme has less residual errors than the Hamming product code enabling reliable transmission at lower link swing voltage. Further, the scheme reduces the power consumption of NoC interconnects up to 71% as compared to Hamming product code with a marginal increase in codec delay and thus router delay. TEC scheme performs well in high noise environment with no delay penalty associated with retransmission.

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2019

R. H., Adithi, R., M. Vinodhini, and Jayasree M. Oli, “2D Mapping Robot using Ultrasonic Sensor and Processing IDE”, 2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN), 2019.[Abstract]


Map building is a vital organ of today's satellite navigation. It is of high use for military operations prior to stealth attacks. In this paper, we present a low-cost solution to building maps of stationary objects. It involves a single ultrasonic sensor mounted on a 180 degree rotating shaft. Readings are taken at regular intervals of time over two sweeps. The algorithm merges the reading of ultrasonic sensor into a semi-circular scalable map. This paper also discusses the algorithms and the mathematics involved. Additional features discussed are motion detection using Passive Infrared sensor and Bluetooth navigation. Our implementation has reduced the computational requirements due to reduced hardware and simplicity of map building algorithm. The resulting graph plots both stationary and moving objects.

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2019

R. Naik, Vaishnavi, S., Jayasree M. Oli, and M. Vinodhini, “Anti-Hijacking system using Raspberry Pi”, 2019 International Conference on Smart Systems and Inventive Technology (ICSSIT), 2019.[Abstract]


With the increase in population, the time taken for the commute from one place to another is extremely important. As such, air travel has been the most preferred mode of transport due to its ability to cover large distances in short periods of time. As a result, it becomes very important to ensure the safety of passengers. As seen in a few instances in the past, lives have been put in jeopardy and extensive damage has been done both in terms of capital and people. We propose a proof of concept for an anti-hijacking system based on the ubiquitous RFID technology.

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2018

D. Sandeep and M. Vinodhini, “Route on Fly Network-on-Chip Router Design with Soft Error Tolerance”, International Conference on Intelligent Computing (ICIC) 2018, 2018.

2018

M. Vinodhini and Dr. N.S. Murty, “Reliable low power NoC interconnect”, Microprocessors and Microsystems, vol. 57, pp. 15-22, 2018.[Abstract]


Information communicated through Network on Chip (NoC) in System on Chip (SoC) is highly prone to different sources of noise, like coupling, radiation and electromagnetic interference. The outcome is multi-bit errors, which can either be random or burst. As the demand for reliable NoC increases, optimal error correcting coding techniques become imperative for SoC and various multi-core and many-core architectures. A novel Multi-bit Error Correcting Coding with Reduced Link Bandwidth (MECCRLB) is proposed to achieve reliable data transmission through NoC. The proposed technique corrects burst error of four bits or random error of eleven bits or combined burst and random errors of total four bits for an input flit size of 32 bits. Analytical model based performance estimation for coding technique is extensively used in NoC. Reliability, link swing voltage and link power consumption are estimated using analytical model for the proposed MECCRLB coding technique. All the results obtained for MECCRLB coding technique are compared with Hamming product code with Type II HARQ. Estimated results show that at a probability of residual error of 10−25, the link swing voltage and the link power are reduced by 30% and 75% respectively. Results obtained from simulation followed by synthesis indicate that there is a reduction of 65%, 44%, 27%, 28% and 49% in bit overhead, NoC router area, NoC router power, codec power and codec area respectively. Furthermore, MECCRLB coding technique achieves higher error correction capability and reduces the need for retransmission. This signifies that the proposed coding technique outperforms Hamming product code with Type II HARQ in reliability, area and power. © 2017 Elsevier B.V.

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