Qualification: 
M.Tech
m_vinodhini@blr.amrita.edu

M. Vinodhini currently serves as Assistant Professor(Sr.Gr) at department of Electronics and Communication, Amrita School of Engineering. She is currently pursuing her Ph. D. 

Publications

Publication Type: Conference Paper

Year of Publication Publication Type Title

2018

Conference Paper

S. U. Himaja, M. Vinodhini, and Dr. N.S. Murty, “Multi-Bit Low Redundancy Error control with Parity Sharing for NoC Interconnects”, in International Conference on Communication and Electronics Systems (ICCES) 2018, PPG Institute of Technology, Coimbatore, 2018.

2018

Conference Paper

D. Sandeep and M. Vinodhini, “Route on Fly Network-on-Chip Router Design with Soft Error Tolerance”, in International Conference on Intelligent Computing (ICIC) 2018, Amrita School of Engineering, Bengaluru, 2018.

2018

Conference Paper

S. T. Teja, Narayana, T. V. V. Saty, M. Vinodhini, and Dr. N.S. Murty, “Joint Crosstalk Avoidance with Multiple Bit Error Correction Coding Technique for NoC Interconnect”, in 7th IEEE International conference on Advances in Computing, Communications and Informatics (ICACCI), PES Institute of Technology, Bengaluru, South campus, India, 2018.

2017

Conference Paper

M. Moulika, M. Vinodhini, and Dr. N.S. Murty, “Data Flipping Coding Technique to Reduce NOC Link Power”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, Coimbatore, India, 2017.[Abstract]


Power consumed by Network on Chip (NoC) plays significant role in the power budget of the System on Chip (SoC). In NoC, links consumes almost quarter of the power. Transition count in the link have to be reduced to reduce the switching activity and hence its dynamic power. Many techniques have been introduced to reduce the transition count. This paper presents a unique data coding technique through which the transition count can be reduced in parallel data transmission. This technique reduces an average of 61.42 percentage of link power with less area compared to quadro and multi coding techniques. The proposed technique, which is applicable for any data width, achieves 17% power saving of the total network used for demonstration.

More »»

2017

Conference Paper

O. L. M. Srrayvinya, M. Vinodhini, and Dr. N.S. Murty, “A Unique Low Power Network-an-Chip Virtual Channel Router”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, 2017.[Abstract]


IP cores on a chip have been drastically increasing with technology scaling. Integration of these cores on a single chip has been a challenge and Network on Chip (NoC) is the cognitive solution to this due to its faster data transmission, smaller area and lower power consumption. Routers constitute a significant part of NoC. It is imperative to design a router that is area and power efficient. The proposed router utilizes the concept of acyclic sorting operation, which replaces the cyclic round robin arbitration to obtain a low power network on chip router architecture, and this architecture is described in detail in this paper. This design achieves 18.03% decrease in area and 24.27% decrease in power with a marginal 16.41 % increase in delay when compared with the Shield router architecture.

More »»

2017

Conference Paper

M. Vinodhini and Dr. N.S. Murty, “Merged arbitration and switching techniques for network on chip router”, in 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS), 2017.[Abstract]


In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is the router which dominants the performance of NoC. A baseline router incorporates the FIFO (First In First Out) buffers, the routing computation logic, the arbiter and the crossbar switch fabric. In this paper, we propose different techniques of merging arbitration and switching functionalities accomplished in wormhole NoC router. Proposed microarchitectures for merging these functionalities are Merged Arbitration and Switching (MAS) microarchitecture based on multiplexer reorganization, Pipelined Merged Arbitration and Switching (PMAS) microarchitecture based on Pipelining and Wave-pipelined Merged Arbitration and Switching (WMAS) microarchitecture based on Wave-pipelining. Synthesis results show that the MAS microarchitecture outperforms the Merged ARbiter and multipleXer (MARX) microarchitecture in area and power consumption by 21.8% and 39.5% respectively. Simulation results show that the PMAS and WMAS microarchitectures outperform MARX microarchitecture in throughput by 40% and 60% respectively at a marginal cost of area and power consumption. Therefore, the benefits of using MAS microarchitecture in wormhole NoC router is low area and power consumption and PMAS or WMAS microarchitecture is high throughput. More »»

2017

Conference Paper

S. Tambatkar, Menon, S. N., Sudarshan, V., M. Vinodhini, and Dr. N.S. Murty, “Error detection and correction in semiconductor memories using 3D parity check code with hamming code”, in 2017 International Conference on Communication and Signal Processing (ICCSP), 2017.[Abstract]


Data stored in memory or buffer needs Error Detection And Correction (EDAC). Errors occur due to supply voltage fluctuations and/or noise due to electromagnetic interference or external radiation. These errors could be either temporary or permanent. In this paper, a EDAC method is proposed to detect and correct errors based on 3D parity check. In the encoder, the data bits are arranged in a matrix format and then parity bits are calculated for each row, column and diagonal. Errors present in parity bits are detected and corrected using Hamming code. Regeneration of data bits and Syndrome calculation at the decoder helps in detecting and correcting the error bits in the data. The 3D Parity check code can correct up to 3 bits of any combination of errors in the data and the Hamming code can correct up to 3 bits in the parity, if they occur in specific combinations. Thus, this method can detect and correct errors in both data and parity bits. This method achieves higher reliability by having a slight tradeoff in area and power consumption compared to other similar methods.

More »»

2017

Conference Paper

P. Raha, M. Vinodhini, and Dr. N.S. Murty, “Horizontal-vertical parity and diagonal hamming based soft error detection and correction for memories”, in 2017 International Conference on Computer Communication and Informatics (ICCCI), 2017.[Abstract]


External radiations create soft errors which are turning into an undeniable critical issue. Customarily, Single Error Correction (SEC) code which can detect and correct 1-bit error per memory word is used to rectify soft errors. As errors turn out to be more common, the SEC methodology becomes inefficient. In this paper, Horizontal-Vertical Parity and Diagonal Hamming (HVPDH) method is proposed for detection of up to 8-bit errors and correction of 1-bit error, all combinations of 2-bit errors and most combinations of 3, 4 and 5-bit errors for memories. The aim here is to incorporate an encoder and decoder which will be effective in detecting and correcting errors. The encoder and decoder use three parity sets, namely horizontal, vertical and grouped diagonal Hamming parities. As per the analysis, higher code rate is achieved by using HVPDH method in memories when compared to the existing methods. More »»

2015

Conference Paper

M. Vinodhini, Lillygrace, K., and Dr. N.S. Murty, “A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.[Abstract]


This paper proposes fault tolerant Network on Chip (NoC) architecture which enables switching of error control coding scheme present in data link layer and network layer as needed, depending upon the rate of error at runtime. The proposed Joint Crosstalk Avoidance-Five Bit Error Correction-Six Bit Error Detection (JCA-FBEC-SBED) error control coding scheme is used in both the layers. This scheme provides crosstalk avoidance and also random and burst error correction up to 5 bits and detection up to 6 bits. The error detection outcomes at all routers in the path are recorded in the error information flit. With the help of error information flit, the error rate is calculated in the destination network interface. The calculated error rate is compared with two threshold values selected based upon the traffic pattern used. If the error rate is less than the lower threshold value, only network layer error control coding scheme is activated. If the error rate is in between the lower and higher threshold values then the error control scheme present in both network layer and datalink layer will be activated, but the error control scheme present in data link layer is activated only in the alternate routers present in the routing path. If the error rate crosses higher threshold value, error control coding scheme present in both the layers will be activated. The proposed JCA-FBEC-SBED error control coding scheme has higher reliability in terms of error detection and correction, when compared to other error control coding schemes with trade-off in delay, area and power consumption. The proposed router architecture has reduced delay and slight increase in area and power consumption of 2.1% and 5.8% respectively, when compared to the runtime adaptive scrubbing router. Our proposed fault tolerant NoC architecture theoretically provide higher data transfer reliability and energy efficiency when compared to other double layer runtime adaptive fault tolerant NoC architectures. The runtime adaptive error control reduces the overall power consumption of the NoC architecture even though JCA-FBEC-SBED decoder consumes more power compared to other schemes. © 2015 IEEE.

More »»

2015

Conference Paper

Ha Kalwad, Neeharika, Sb, Divya, Sc, M. Vinodhini, and Dr. N.S. Murty, “Merged switch allocation and transversal with dual layer adaptive error control for Network-on-Chip switches”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.[Abstract]


In this paper, we propose a Network on Chip router architecture with increased reliability, energy efficiency and with reduced area overhead. The proposed router architecture model adjusts dynamically to the error control strengths of the layers of NoC. In this paper, we target to optimize the combined operations of arbiter and multiplexer by using a Merged Arbiter Multiplexer (MARX) along with a dual layer cooperative error control protocol. By doing so, the number of pipe line stages, area and power consumed is reduced. We use XY Routing algorithm to send data from one router to the other when these routers are placed in network architecture. The proposed model outperforms the dual layer error control model without MARX unit. The router architecture with MARX unit has 22.7% less area and 2.4% less energy consumption than router architecture without MARX unit but has moderate increase in the delay. © 2015 IEEE.

More »»