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Publication Type : Conference Paper
Publisher : 2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)
Source : 2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), IEEE, Udupi, India (2020)
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2020
Abstract : Advancement in Complementary Metal Oxide Semiconductor (CMOS) technology causes Multiple Cell Upsets (MCUs). Due to the radiation particles, MCUs had been a challenging issue for data storage in memory for different applications. One of the techniques which is more often used to protect memories is Error Correction Code, because of their low complexity encoding and decoding. Generally, MCUs affect adjacent bits stored in the memory. Therefore, the technique which would detect and correct the adjacent bits as many as possible would be a productive technique. The only drawback with Matrix based code is the required number of parity bits which is used to support error correction in memories is very high. To resolve the drawback, we worked to minimise the number of parity bits in this paper. The proposed technique has equal error correction capability with smaller count of parity bits as compared to other existing techniques. Total parity bits has been reduced by 30% and area, power and delay time has been reduced by 1.12%, 33.59%, 55.46% respectively. These parameters make the proposed technique an efficient and productive one for protecting memories. This technique can be used in applications which have very strict constraints Of parity bits and speed.
Cite this Research Publication : K. Nandan Kumar, Reddy, N. V. S. Anvesh, Shanmukh, P., and M. Vinodhini, “Matrix based Error Detection and Correction using Minimal Parity Bits for Memories”, in 2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), Udupi, India, 2020.