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Publication Type : Conference Paper
Publisher : 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA)
Source : 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), IEEE, Coimbatore, India (2019)
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2019
Abstract : Matrix based computations are a typical way to implement many day-to-day systems. In particular, matrix vector multiplication has been implemented to provide solutions to wide range of contemporary issues. The work proposed in this paper is to detect and locate errors present in the results of a matrix vector multiplication. In matrix vector multiplication, computations are run in parallel. Categorically, this work aims to provide a mechanism to use checksum, linear binary coding technique to identify underlying faults in computational results. The necessary mathematical formulations have been derived and the design is synthesised to estimate the impact of efficient multi bit error tolerance for matrix vector multiplication. It is noticed that multi bit error tolerance for matrix vector multiplication is achieved with power optimisation compared to single bit error tolerance.
Cite this Research Publication : P. G. Hitesh, Venkatesh, P., P Reddy, S. Thirumal, and M. Vinodhini, “Efficient Multi-Bit Error Tolerant design for MVM”, in 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2019.