Publication

Abstract : The article introduces a novel comparison-free parallel hardware sorting engine designed to manage duplicate elements alongside the existing comparison-free parallel sorter. This engine achieves linear sorting delay of O(N) clock cycles or fewer, sorting data set of N, n-bit unsigned elements efficiently with any number of identical elements with degree k=4. Remarkably, it can process N data elements with varying duplicity rates under O(N) clock cycles. The architecture uses basic logic components to create n-symmetric cascaded blocks. To handle any number of identical elements in the data set that needs to be sorted and to sort all the elements efficiently, the largest element detector of the existing parallel sorter is improvised. The synthesis results indicate that despite a small increase in power consumption, area, and resource usage, the proposed sorter offers a significant advantage by effectively handling duplicity. This capability is particularly beneficial as it ensures the accuracy and reliability of sorting processes, even though it necessitates minor compromises in other performance parameters. The trade-off between slightly increased resource demands and the ability to manage duplicate entries highlight the importance of robustness and precision in the proposed solution, making it a valuable contribution to the field.