Qualification: 
Ph.D, M.E, BE
c_paramasivam@blr.amrita.edu
Phone: 
+91 9994073577

Dr. C. Paramasivam serves as Assistant Professor (Sr. Gr.) at the Department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru. Prior to joining Amrita, he was working in the department of Electronics and Communication Engineering, K. S.Rangasamy College of Technology, Namakkal, Tamil Nadu for 12 years. He holds a Ph. D. degree in 'High Performance VLSI Architecture Design for DSP Applications' from Anna University, M. E. degree in VLSI Design from Anna University and B. E. degree in Electrical and Electronics from Bharathiar University. He has more than 28 publications in International Journals and Conferences. His area of research includes, Digital VLSI Design, Low Power VLSI Design, VLSI Architecture Design for Digital Signal Processing Application, SoC design, Wireless Sensor Networks and LTE Architecture Design for 5G Technology. He has carried out a significant role as Chief Coordinator in Center for VLSI available in K.S. Rangasamy College of Technology, Coordinator for IETE, Mentor for NPTEL online course, Department Coordinator for workshop conducted through NMEICT project, IIT Kharagpur, etc. He has guided 14 PG projects and 14 UG Projects. He is a Life Member of Indian Society for Technical Education (ISTE), The Institution of Electronics and Telecommunication Engineers (IETE) and Indian Society of Systems for Science & Engineering (ISSE).

Education

  • 2018: Ph. D. 
    Anna University, Chennai
  • 2007: M. E. (VLSI Design)
    Anna University, Chennai
  • 2004: B. E. 
    Bharathiar University, Coimbatore

Publications

Publication Type: Journal Article

Year of Publication Title

2018

Paramasivam C., Aravindhan, E., R. priya, H., Hema, M., and A. singh, C., “FPGA Based Real Time Bluetooth Communication for Tele health, Household Security and Industry Safety”, Proceedings on International Conference on Modern Global Research in Engineering & Technology (ICMGRET), vol. Vol.1, p. Page 44, 2018.[Abstract]


Real-time Bluetooth monitoring system which can used to boost the people’s health guarantee, Home security and industrial safety using android smart phone is presenting in this paper. This technology is primarily used to detect the pulse of patient, smoke level in home and temperature of the industry, the monitor data is received by end user using Bluetooth wireless communication device. Android based smartphone is the first choice of people as these devices are established with large compatibility and mobility, whereas they are low cost devices. FPGA based embedded systems have faster processing capability, low power usage and is reconfigurable as per requirement. In this paper we introduce the design and implementation of the real time remote monitoring using Bluetooth between FPGA based embedded system and android smartphones. This system is very useful where 24 hours real time remote monitoring for reporting and vigilance is required. Advantages of this system is user-friendly interface and is comfortable to end user.

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2017

Paramasivam C., .K, S., .K, S., .N, S., R, R., and Paramasivam, K. & C., “Voice Controlled Home Appliances Using Embedded System”, International Journal of Emerging Technology in Computer Science and Electronics, vol. 24, 05 vol., pp. pp. 28870-28875, 2017.

2016

Paramasivam C. and Jones, M. M., “A low complexity and reconfigurable SDF-FFT processor for Wireless Applications”, Proceedings on 3rd IEEE International Conference on Innovations in Information Embedded and Communication Systems(ICIIECS), vol. 3, pp. Pages 52-59, 2016.

2016

Paramasivam C. and Suganya, V., “Parallel pipelined FFT architecture for real valued signals”, Proceedings on IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), vol. 1, pp. Pages 2201-2203., 2016.

2015

Y. T and Paramasivam C., “Implementation of CORDIC look ahead based VLSI architecture for Kaiser Bessel window techniques in spectral analysis”, International journal of Applied Engineering Research, vol. vol.10, no. 38 vol., pp. pp. 28870-28875, 2015.

2015

Kchandrabos K and Paramasivam C., “CORDIC based Pipelined Parallel Architecturte for RFFT and RIFFT”, International journal of Applied Engineering Research, vol. vol.10, no. 38 vol., pp. pp. 28804-28809, 2015.

2015

Paramasivam C. and Jayanthi, K. B., “Modified Scaling-Free CORDIC Based Pipelined Parallel MDC FFT and IFFT Architecture for Radix-22 Algorithm”, World Academy of Science, Engineering and Technology, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering, vol. vol.9, 12 vol., pp. pp. 1379-1385., 2015.[Abstract]


An innovative approach to develop modified scaling free CORDIC based two parallel pipelined Multipath Delay Commutator (MDC) FFT and IFFT architectures for radix 22 FFT algorithm is presented. Multipliers and adders are the most important data paths in FFT and IFFT architectures. Multipliers occupy high area and consume more power. In order to optimize the area and power overhead, modified scaling-free CORDIC based complex multiplier is utilized in the proposed design. In general twiddle factor values are stored in RAM block. In the proposed work, modified scaling-free CORDIC based twiddle factor generator unit is used to generate the twiddle factor and efficient switching units are used. In addition to this, four point FFT operations are performed without complex multiplication which helps to reduce area and power in the last two stages of the pipelined architectures. The design proposed in this paper is based on multipath delay commutator method. The proposed design can be extended to any radix 2n based FFT/IFFT algorithm to improve the throughput. The work is synthesized using Synopsys design Compiler using TSMC 90-nm library. The proposed method proves to be better compared to the reference design in terms of area, throughput and power consumption. The comparative analysis of the proposed design with Xilinx FPGA platform is also discussed in the paper.

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2014

Paramasivam C. and S, A., “Modified Scaling-Free Micro-rotation based Circular CORDIC Algorithm using Taylor Series Expansion of Sine and Cosine”, Proceedings on IEEE International Conference on Innovations in Engineering and Technology (ICIET), vol. Vol.1, pp. Pages 768-772, 2014.

2013

Paramasivam C. and C. Murugan, A., “Energy Efficient FPGA based VLSI architecture for MPEG-2 Video Decoding”, Proceedings on International conference on Futuristic Trends in Electronics Engineering (ICFTEE), vol. 1, pp. Pages 366-370, 2013.

2013

B. Pushparaj and Paramasivam C., “High performance and low power modified radix-25 FFT architecture for high rate WPAN application”, Proceedings on IEEE International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), vol. 1, pp. Pages 1-4, 2013.

2013

S. .Venkatlakshmi, .Venkatlakshmi, S., Revathi, S., Arul, E. M. S., and Paramasivam C., “Industrial Process Management Using LabVIEW”, IOSR Journal of Electronics and Communication Engineering, vol. 5, pp. 46-56, 2013.[Abstract]


Nowadays process management is a tedious task in the industry. We plan to propose a LabVIEW based intelligent multi parameter monitoring system designed using RS232 and Microcontroller aids in the measurement and control of various Global Parameters. For data collection in the industry is a difficult task in real time execution of events with industrial process control and automation. We proposed two slaves for measuring various industrial parameters to monitor and control industrial process. Data acquired from each slave is processed and sent to Master that compile data received from different slaves and send this information to the system configured with LabVIEW platform. This enables us to view and track the online changes encountered in the particular parameter of all the parameters. One of the main advantages of this proposal is, it allows us to view all the parameter readings simultaneously on the front panel in LabVIEW. The Graph drawn on the front panel keeps on tracking the changes on the parameter. The parameters supported by this project includes: current, voltage, temperature, frequency, light intensity, logic switches, water level identifier, and alarm. This Project can be implemented in any of the process industries where there is a need for Simultaneous and fast acquiring of data and control.

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2012

A. C. Murugan and Paramasivam C., “Energy Efficient FPGA Based VLSI Architecture for Mpeg-2 Audio/Video Decoding”, CIIT International Journal of Programmable Device Circuits and Systems, vol. 4, 2 vol., 2012.

Publication Type: Conference Proceedings

Year of Publication Title

2018

A. Meena, Anbarasan, K., Badhrinaathan, S. B., G. Ranjith, M., and Paramasivam C., “RFID based navigation system for unmanned material handling vehicle using FPGA”, Proceedings on International Conference on Modern Global Research in Engineering & Technology (ICMGRET). IEEE, Gujarat, India, 2018.[Abstract]


The paper reports a navigation system which uses passive RFID tags for localization. The entire terrain is mapped into a grid of nodes each containing a tag that refers to a specific location on the terrain which is sensed by the vehicle using the onboard compatible RFID reader. These tags provide the vehicle with the sense of its position and orientation on the terrain. The system uses Flood fill algorithm to generate the shortest path to the destination while also maneuvering the obstacles. During the course of traversing the path, on reading each tag, the system ensures that the location read from tag is consistent with the generated route. On the event of any mismatch, a new path to the destination is generated, empowering the system with error detection and correction capabilities. The system uses FPGA as the processing unit on account of its flexibility and high parallel processing capabilities.

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2017

S. K, K, S., N, S., K, R., and Paramasivam C., “IOT based smart surveillance of human health system”, Proceedings on National conference on Recent advancement and effectual researches in electrical engineering , vol. 1. p. Page 6., 2017.

2016

Paramasivam C. and B, J. K., “An In-Place FFT and IFFT architecture for radix-22 algorithm using modified scaling free CORDIC”, Proceedings on IEEE sponsored 3rd International Conference on Electronics and Communication Systems, vol. 5. pp. Pages 3526-3531, 2016.

2015

M. Manikandan and Paramasivam C., “Area and Time Efficient FFT Architecture Using Hardwired Pre-Shifted Bi-Rotation Cordic Design”, International Conference on Innovations in Engineering and Technology (ICIET), vol. 1. pp. 260-265, 2015.

2015

Paramasivam C. and T, Y., “Implementation of hyperbolic CORDIC-based VLSI architecture for Kaiser-Bessel window techniques in spectral analysis”, Proceedings on DRDO Sponsored 2nd IEEE International conference on Innovations in Information, Embedded and Communication Systems(ICIIECE’15), vol. 1. 2015.

2015

Paramasivam C. and K, Kchandrabos, “CORDIC Based Pipelined Parallel Architecture for RFFT and RIFFT”, Proceedings on International Conference on Advances in computing, control, communication, automation and structural engineering (ACCCAS-2015), vol. 1. pp. Pages 350-357, 2015.

2015

Paramasivam C. and KB, J., “Modified Scaling –Free CORDIC based in place FFT and IFFT architecture for radix-22 algorithm”, Proceedings on International Conference on Innovations in computer science and Information Technology(ICICSIT), vol. 1. pp. Pages 114-118, 2015.

2014

A. S. and Paramasivam C., “Modifid Scaling-Free based Circular CORDIC algorithm using Taylor Series Expansion”, International conference on Innovations in Information, Embedded and Communication Systems, vol. 1. pp. 861-865, 2014.

2014

M. Manikandan and Paramasivam C., “Area and Time Efficient Hardwired Pre –Shifted Bi-Rotation CORDIC Design”, Proceedings on 3rd IEEE International Conference on Communication and Signal Processing, vol. 1, Pages 1740-1745 vol. 2014.

2013

A. C. Murugan and Paramasivam C., “Energy Efficient VLSI architecture for MPEG-2 Video Decoding”, Proceedings on International conference on Computing, Communication and Applications(ICCCA), vol. 1. p. Pages 100, 2013.

2011

Paramasivam C. and Punithavathi, A., “Design of Low Power Coarse Grained Reconfigurable Architecture by Reusable Context Pipelining”, Proceedings on Fourth National conference on Computer, Communication and networking engineering(NCCCN’11), vol. 1. p. Page 10, 2011.

2010

Paramasivam C. and Ramkumar, N., “Low Power hardware architecture for VBSME using PIXEL truncation”, Proceedings on National conference on Recent advancements in engineering & technology, vol. 1. pp. Page 304-309, 2010.

2009

Paramasivam C., “Minimization of area in DSP application based high speed arithmetic circuits”, Proceedings on Silver Jubilee conference on communication technologies and VLSI design, vol. 1. pp. Pages 350-355, 2009.

2009

S. Mahendran and Paramasivam C., “An Improved auto scan design approach for sequential circuits”, Proceedings on National conference on Advanced Communication and Computing, vol. 1. p. Page 14., 2009.

2009

Paramasivam C., “Area Minimization in DSP Application based High speed arithmetic circuits”, Proceedings on Second International conference on Signal and Image Processing (ICSIP), vol. 1. pp. Pages 215-220., 2009.

2008

Paramasivam C., “Reverberant speech enchancement using two stage algorithm”, Proceedings on Third National conference on recent trends in Electrical, Electronics, Instrumentation & Communication Engineering, vol. 1. pp. Pages 441-448, 2008.

2007

Paramasivam C., ,, and Rameshwaran, M., “Minimization of silicon area in high speed arithmetic circuits”, Proceedings on National conference on Modeling, Analysis & Simulation of Computers and Telecommunication systems(MASCOT), vol. Vol.1. pp. Pages 150-154, 2007.

2007

Paramasivam C., Kalavathidevi, T., and Rameshwaran, M., “Low power design of high speed arithmetic circuits”, Proceedings on Second National conference on Trends and development in VLSI and embedded systems, vol. 1. 2007.

Publication Type: Conference Paper

Year of Publication Title

2015

Paramasivam C., “High throughput feed forward pipelined parallel architecture for FFT and IFFT”, in 2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS), Coimbatore, India, 2015.[Abstract]


This paper presents a novel approach to develop pipelined architectures for fast Fourier transform (FFT) and Inverse fast Fourier transform (IFFT). For reducing area and time complexity, the architectures use hard wired Twiddle factor storage and new switching circuit for complex multiplication and that is employed in four point FFT/IFFT architectures. Pipelined Architectures for complex valued fast Fourier transform and Inverse fast Fourier transform are derived. This projected design is intended based on feed forward designs and may be extended to any radix 2<sup>n</sup> based FFT/IFFT algorithm to extend the throughput. The projected FFT/IFFT design was synthesized by Synopsys design Compiler using the TSMC 90-nm library, and also the projected designs provide less latency and high Throughput than the reference FFT design. The design also synthesized for various Xilinx field-programmable gate-array platforms that also shows comparable results.

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2014

M. M and Paramasivam C., “Area and time efficient hardwired pre -shifted bi-rotation CORDIC design”, in International Conference on Communication and Signal Processing, ICCSP 2014 - Proceedings, 2014.[Abstract]


This paper presents CORDIC based feed forward FFT architecture. It is used to implement the pipeline FFT hardware architecture. The radix 2k feed forward FFT architecture can be used for the any number of parallel sample which is power of two. It can be achieved the high throughput and low hardware requirement. The hardwired pre shifted bi- rotation cordic technique for barrel-shifter of proposed circuit. Here two proposed CORDIC cells are used to the fixed angle rotations. This cells going to implement the micro rotations and scaling interleaved, it’s implemented the two stages. The cascade proposed the bi-rotation CORDIC for higher throughput and reduced latency implementation. This method proposed optimized set of micro rotations for fixed and known angles. Shift and add circuits are used to implement the scaling factor. Fixed means square error used for analysis and reduced the error in this method. Synthesized the proposed CORDIC cells by Synopsys Design Compiler using TSMC 90-NM library, and shown that the proposed designs offer higher throughput, less latency and less area-delay product than the reference CORDIC design for fixed and known angles of rotation. We find similar results of synthesis of different Xilinx field-programmable gate-array platforms.

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2013

A. Malashri and Paramasivam C., “Low power and memory efficient FFT architecture using modified CORDIC algorithm”, in 2013 International Conference on Information Communication and Embedded Systems (ICICES), 2013.[Abstract]


This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. CORDIC is implemented by a simple hardware through repeated shift-add operations Low power is achieved by the using the Coordinate Rotation Digital Computer algorithm in the place of conventional multiplication and furthermore, dynamic power consumption is reduced with no delay penalties.

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